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In this paper, graphene field effect transistors (GFETs) with the top-gate structure are taken as the research object. The electrical stress reliabilities are studied under different bias voltage conditions. The electrical pressure conditions are gate electrical stress (VG = –10V, VD = 0V and VS = 0V), drain electric stress (VD = –10V, VG = 0V and VS = 0V), and electrical stresses applied simultaneously by gate voltage and drain voltage (VG = –10V, VD = -10V, VS = 0V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage VDirac degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressures, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions have varying effects on the drift direction and degradation of VDirac: gate electrical stress and drain electrical stress cause VDirac drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate voltage and drain voltage, leading to VDirac degradation of GFETs. An analysis of the causes indicates that different electrical stresses produce different electric field directions in the device, which can affect the carrier concentration and movement direction. Electrons and holes in the channel are induced and tunnel into the oxide layer, and they are captured by trap charges in the oxide layer and at the interface between graphene and oxide, forming oxide trap charges and interface trap charges. This is the main reason for reducing carrier mobility of GFET. Different electric field directions under different electric stresses produce positively charged trap charges and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of VDirac drift in GFETs. When both trap charges coexist, they have a canceling effect on the VDirac drift of the GFETs. Finally, by combining TCAD simulation the simulation model of the influence of electrical stress induced trap charge on the VDirac generation of GFET is further revealed. The result demonstrates that the differences in the type of trap charge banding have different degradation effects on the VDirac of GFETs. The related research provides data and theoretical support for putting graphene devices into practical application .
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Keywords:
- graphene field effect transistors /
- electrical stress /
- VDirac /
- carrier mobility
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图 1 器件结构示意图
Figure 1. Device structure diagram.
图 2 GFET的转移特性曲线在不同漏极电压下的变化趋势
Figure 2. The variations of the transfer characteristic curve of GFET under different drain voltages.
图 3 栅极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势
Figure 3. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under gate voltage bias condition.
图 5 栅极和漏极电压同时施加的电应力下, GFET转移特性曲线随电应力累积时间的变化趋势
Figure 5. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under the condition of electrical stress applied by both the gate and drain voltages.
图 4 漏极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势
Figure 4. Variations of GFET transfer characteristic curves with the accumulation time of electrical stress under drain voltage bias conditions.
图 6 VDirac随着电应力累积时间的变化趋势
Figure 6. The variations of VDirac with the accumulation time of electrical stress.
图 7 载流子迁移率随电应力累积时间的变化趋势 (a)空穴迁移率随电应力累积时间的变化趋势; (b)电子迁移率随电应力累积时间的变化趋势
Figure 7. The variations of carrier mobility with the accumulation time of electrical stress: (a) The variations of hole mobility with the accumulation time of electrical stress; (b) the variations of electron mobility with the accumulation time of electrical stress.
图 8 TCAD仿真结果 (a)带正电荷的固定陷阱电荷对GFET转移特性曲线的影响; (b)带负电荷的固定陷阱电荷对GFET转移特性曲线的影响; (c)带正电荷和带负电荷的固定陷阱电荷同时对GFET转移特性曲线的影响
Figure 8. TCAD simulation results: (a) Effect of a positively charged fixed trap charge on the transfer characteristic curve of GFET device; (b) effect of negatively charged fixed trap charge on the transfer characteristic curve of GFET device; (c) the effect of both positively charged and negatively charged fixed trap charges on the transfer characteristic curve of GFET devices.
表 1 电应力实验测试条件
Table 1. Electrical stress test conditions.
偏置电压条件 电应力测试时间点 转移特性曲线测试条件 栅极电应力(VG = –10 V, VD = 0 V, VS = 0 V) 0 s, 100 s, 300 s, 500 s, 1000 s VG 从–5 V扫到5 V VD 为20 mV VS 接地 漏极电应力 (VG = 0 V, VD = –10 V, VS = 0 V) 栅极电压与漏极电压同时施加的电应力
(VD = –10 V, VD = –10 V, VS = 0 V)
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