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本文以顶栅结构的石墨烯场效应晶体管（graphene field effect transistors,GFET）为研究对象，开展了不同偏置电压条件下的电应力可靠性研究。试验结果表明：在不同偏置电压条件的电应力作用下，GFET的载流子迁移率随着电应力时间的增加均不断的退化，而不同偏置电压条件的电应力对狄拉克电压（VDirac）的漂移方向和退化程度的影响不同；栅极电应力与漏极电应力造成器件的VDirac漂移方向相反，且栅极电应力要比栅极和漏极电压同时施加的电应力导致GFET的VDirac退化程度更加明显。分析原因表明：不同偏置电压条件下的电应力试验在器件中产生的电场方向不同，从而会影响载流子浓度和移动方向。诱导沟道中的电子和空穴隧穿进入氧化层，被氧化层中缺陷和石墨烯\氧化层界面处的陷阱俘获，形成氧化物陷阱电荷和界面陷阱电荷，从而导致GFET的载流子迁移率降低。而电应力产生陷阱电荷的带电类型差异是造成VDirac漂移方向不同的主要原因。论文结合TCAD仿真，进一步揭示了电应力感生陷阱电荷对GFET的VDirac产生影响仿真模型。相关研究对石墨烯器件的实际应用提供数据和理论支撑。In this paper, graphene field effect transistors (GFET) with the top-gate structure are taken as the research object. Conducted electrical stress reliability studies under different bias voltage conditions. The electrical pressure conditions are Gate Electrical Stress (VG=-10V, VD=0V, VS=0V), drain electric stress (VG=0V, VD=-10V, VS=0V), and Electrical stresses applied simultaneously by gate and drain voltages (VG=-10V, VD= -10V, VS=0V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage VDirac degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressure conditions, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions affect the drift direction and degradation of VDirac differently: Gate electrical stress and drain electrical stress cause VDirac drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate and drain voltages leading to VDirac degradation of GFETs. An analysis of the causes suggests that different electrical stress conditions produce different electric field directions in the device, which can affect the carrier concentration and direction of movement. Electrons and holes in the channel are induced to tunnel into the oxide layer and are captured by trap charge in the oxide layer and at the graphene\oxide interface, forming oxide trap charges and interface trap charges. This is the main reason for the reduced carrier mobility of GFETs. Different electric field directions under different electric stress conditions produce positively charged and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of VDiracdrift in GFETs. When both trap charges are present at the same time, they have a canceling effect on the amount of VDiracdrift of the GFETs. Finally, the paper combines TCAD simulation, further revealing the simulation model of the impact of electrical stress induced trap charge on the VDiracgeneration of GFETs. The result demonstrates that differences in the type of trap charge banding have different degradation effects on the VDirac of GFETs. The related research provides data and theoretical support for the practical application of graphene devices.
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Keywords:
- graphene field effect transistors /
- Electrical stress /
- VDirac /
- Carrier mobility
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