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Based on the influence of the nonuniform temperature distribution and the inductance effect of the wires on the interconnect delay time, a zero-clock-skew construction method of RLC interconnect clock tree is presented in this paper. The proposed analytical model has closed form expression and takes temperature distribution, inductance effect and unsymmetrical interconnect structure into consideration. Adopting parameters of 65 nm process technology, the proposed model is compared with the other available similar models. Results show that the new model is more accurate with maximum 1% error.
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Keywords:
- RLC /
- temperature distribution /
- unsymmetrical interconnect structure /
- zero-clock-skew point
[1] Wang B H, Mazumder P 2009 Design, Automation and Test in Europe Conference and Exhibition London, UK, April 20-24, 2009 p280
[2] Datta B, Burleson W P 2007 IFIP Int. conf. on Very Large Scale Integration Atlanta, USA, October 15-17, 2007 p258-263
[3] Padmanabhan U, Wang J M, Hu J 2008 IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems 27 1385
[4] Ajami H A, Pedram M, Banerjee K 2001 IEEE Int. conf. on custom integrated circuits San Diego, USA, May 7-9, 2001 p233
[5] Ajami A H, Banerjee K, Pedram M 2005 IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems 24 849
[6] Rosenfeld J, Friedman E G 2007 IEEE Trans.Very Large Scale Integration 15 135
[7] Kim S Y, Wong S S 2007 IEEE Trans. Circuits and Systems I-Reg.Papers 54 2001
[8] Jiang Z, Hu S, Hu J, Li Z, Shi W 2006 Proc. Int. Conf. on Computer-Aided Design San Jose, CA, USA, November 5-9, 2006 p553
[9] Shebaita A, Petranovic D, Ismail Y 2007 Proc. Int. Conf. on Computer-Aided Design San Jose, CA, USA, November 5-9, 2007 p686
[10] Roy A, Chowdhury M H 2008 IEEE Int. Symp. on Circuits and Systems Seattle, WA, USA, May 18-21, 2008 p2426
[11] Alioto M, Palumbo G, Poli M 2009 IEEE Trans. 17 278
[12] Zhu Z M, Hao B T, Qian L B, Zhong B, Yang Y T 2009 Acta Phys. Sin. 58 7130 (in Chinese) [朱樟明、郝报田、钱利波、钟 波、杨银堂 2009 58 7130 ]
[13] Venkatesan R, Davis J A, Meindl J D 2003 IEEE Trans. Electron Devices 50 1081
[14] Zhou M, Liu W, Sivaprakasam M 2005 IEEE Int. Symp. on Circuits and Systems Kobe, Japan, May 23-26, 2005 p1082
[15] Uyemura J P (Translated by Zhou R D) 2004 Introduction to VLSI circuits and systems (1st ed) (Beijing: Publishing House of Electronics Industry) p447 (in Chinese)
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[1] Wang B H, Mazumder P 2009 Design, Automation and Test in Europe Conference and Exhibition London, UK, April 20-24, 2009 p280
[2] Datta B, Burleson W P 2007 IFIP Int. conf. on Very Large Scale Integration Atlanta, USA, October 15-17, 2007 p258-263
[3] Padmanabhan U, Wang J M, Hu J 2008 IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems 27 1385
[4] Ajami H A, Pedram M, Banerjee K 2001 IEEE Int. conf. on custom integrated circuits San Diego, USA, May 7-9, 2001 p233
[5] Ajami A H, Banerjee K, Pedram M 2005 IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems 24 849
[6] Rosenfeld J, Friedman E G 2007 IEEE Trans.Very Large Scale Integration 15 135
[7] Kim S Y, Wong S S 2007 IEEE Trans. Circuits and Systems I-Reg.Papers 54 2001
[8] Jiang Z, Hu S, Hu J, Li Z, Shi W 2006 Proc. Int. Conf. on Computer-Aided Design San Jose, CA, USA, November 5-9, 2006 p553
[9] Shebaita A, Petranovic D, Ismail Y 2007 Proc. Int. Conf. on Computer-Aided Design San Jose, CA, USA, November 5-9, 2007 p686
[10] Roy A, Chowdhury M H 2008 IEEE Int. Symp. on Circuits and Systems Seattle, WA, USA, May 18-21, 2008 p2426
[11] Alioto M, Palumbo G, Poli M 2009 IEEE Trans. 17 278
[12] Zhu Z M, Hao B T, Qian L B, Zhong B, Yang Y T 2009 Acta Phys. Sin. 58 7130 (in Chinese) [朱樟明、郝报田、钱利波、钟 波、杨银堂 2009 58 7130 ]
[13] Venkatesan R, Davis J A, Meindl J D 2003 IEEE Trans. Electron Devices 50 1081
[14] Zhou M, Liu W, Sivaprakasam M 2005 IEEE Int. Symp. on Circuits and Systems Kobe, Japan, May 23-26, 2005 p1082
[15] Uyemura J P (Translated by Zhou R D) 2004 Introduction to VLSI circuits and systems (1st ed) (Beijing: Publishing House of Electronics Industry) p447 (in Chinese)
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