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Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.
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Keywords:
- p-channel metal-oxide-semiconductor /
- negative bias temperature instability /
- process variations /
- threshold voltage
[1] Tibor G, Karina R, Hans R 2014 IEEE Trans. Electron Devices 61 3586
[2] Blat C E, Nicollian E H 1991 J. Appl. Phys. 69 1712
[3] Shigeo O, Masakazu S 1995 J. Appl. Phys. 77 1137
[4] Li Z H，Liu H X，Hao Y 2006 Acta Phys. Sin. 55 820 (in Chinese) [李忠贺, 刘红霞, 郝跃 2006 55 820]
[5] Chen S M, Chen J J, Chi Y Q, Liu F Y, He Y B 2012 Sci. China Ser. E 55 1101
[6] Tsai Y S 2010 IEEE International Reliability Physics Symposium Anaheim, USA, May 2-6, 2010 p665
[7] Cenk Y, Leonhard H, Christoph W, Doris S L 2013 IEEE International Reliability Physics Symposium Monterey, USA, April 14-18, 2013 p2A.4.1
[8] Mahapatra S, Huard V, Kerber A, Reddy V, Kalpat S, Haggag A 2014 IEEE International Reliability Physics Symposium Waikoloa, USA, June 1-5, 2014 p3B.1
[9] Tang H L, Zhuang Y Q, Xi W, Zhang L 2013 J. Huazhong Univ. Sci. Tech. (Natural Science Edition) 41 22 (in Chinese) [汤华莲, 庄奕琪, 席望, 张丽 2013 华中科技大学学报(自然科学版) 41 22]
[10] Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S 2006 Proceedings of the IEEE 2006 Custom Integrated Circuits Conference San Jose, USA, September 10-13, 2006 p189
[11] Pelgrom, Marcel J M, Duinmaijer, Aad C J, Welbers, Anton P G 1989 IEEE J. Solid State Circuits 24 1433
[12] Wen P W, Vijay R, Anand T 2007 IEEE Trans. Device Mater. Reliab. 7 509
[13] Jeppson K, Svensson C 1977 J. Appl. Phys. 48 2004
[14] Van Den Bosch A, Borremans M A F, Steyaert M S J, Sansen W 2001 IEEE J. Solid State Circuits 36 315
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[1] Tibor G, Karina R, Hans R 2014 IEEE Trans. Electron Devices 61 3586
[2] Blat C E, Nicollian E H 1991 J. Appl. Phys. 69 1712
[3] Shigeo O, Masakazu S 1995 J. Appl. Phys. 77 1137
[4] Li Z H，Liu H X，Hao Y 2006 Acta Phys. Sin. 55 820 (in Chinese) [李忠贺, 刘红霞, 郝跃 2006 55 820]
[5] Chen S M, Chen J J, Chi Y Q, Liu F Y, He Y B 2012 Sci. China Ser. E 55 1101
[6] Tsai Y S 2010 IEEE International Reliability Physics Symposium Anaheim, USA, May 2-6, 2010 p665
[7] Cenk Y, Leonhard H, Christoph W, Doris S L 2013 IEEE International Reliability Physics Symposium Monterey, USA, April 14-18, 2013 p2A.4.1
[8] Mahapatra S, Huard V, Kerber A, Reddy V, Kalpat S, Haggag A 2014 IEEE International Reliability Physics Symposium Waikoloa, USA, June 1-5, 2014 p3B.1
[9] Tang H L, Zhuang Y Q, Xi W, Zhang L 2013 J. Huazhong Univ. Sci. Tech. (Natural Science Edition) 41 22 (in Chinese) [汤华莲, 庄奕琪, 席望, 张丽 2013 华中科技大学学报(自然科学版) 41 22]
[10] Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S 2006 Proceedings of the IEEE 2006 Custom Integrated Circuits Conference San Jose, USA, September 10-13, 2006 p189
[11] Pelgrom, Marcel J M, Duinmaijer, Aad C J, Welbers, Anton P G 1989 IEEE J. Solid State Circuits 24 1433
[12] Wen P W, Vijay R, Anand T 2007 IEEE Trans. Device Mater. Reliab. 7 509
[13] Jeppson K, Svensson C 1977 J. Appl. Phys. 48 2004
[14] Van Den Bosch A, Borremans M A F, Steyaert M S J, Sansen W 2001 IEEE J. Solid State Circuits 36 315
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