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Based on dual supply and dual threshold voltages technique, a novel methodology optimizing global interconnect performance in presented in this paper. The new figure of merit (FOM) is first defined as a function of bandwidth, delay and power consumption of global interconnect. Then, the optimal dual voltages can be obtained to save interconnect power by maximizing FOM function within a given delay penalty. Simulations show that in 65 nm technology, for the allowed delay penalties of 5%, 10% and 20%, the proposed methodology saves 27.8%, 40.3% and 56.9% power compared with the case with single supply and single threshold voltages, respectively. It can also be found that more power savings are achieved with the technology improving. The proposed methodology can be used to design and optimize global interconnects.
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Keywords:
- global interconnect /
- dual supply voltage /
- dual threshold voltage /
- power
[1] Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 (in Chinese) [王俊平、郝 跃 2009 58 4267]
[2] Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 (in Chinese) [李 鑫、Janet M Wang、唐卫清 2009 58 3603]
[3] Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 58 2631]
[4] Li X C, Mao J F, Huang H F, Liu Y 2005 IEEE Transactions on Electron Devices 52 2272
[5] Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[6] Banerjee K, Mehrotra A 2002 IEEE Transactions on Electron Devices 49 2001
[7] Naeemi A, Venkatesan R, Meindl J D 2004 IEEE Transactions on Electron Devices 51 980
[8] Mui M L, Banerjee K, Mehrotra A 2004 IEEE Transactions on Electron Devices 51 195
[9] Zhu Z M, Hao B T, Li R, Yang Y T 2010 Acta Phys. Sin. 59 1997 (in Chinese) [朱樟明、郝报田、李 儒、杨银堂 2010 59 1997]
[10] Ku J C, Ismail Y 2007 IEEE Transactions on VLSI Systems 15 963
[11] Zhu Z M, Zhong B, Hao B T, Yang Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明、钟 波、郝报田、杨银堂 2009 58 7124]
[12] Tam K H, Hu Y, He L 2008 IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27 1498
[13] Chang Y C, Tam K H, He L 2005 Proc. ISLPED, San Diego, USA, August 8—10, p137
[14] Diril A U, Dhillon Y S, Chatterjee A, Singh A D 2005 IEEE Transactions on VLSI Systems 13 1103
[15] Bakoglu H B, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990
[16] Chen G, Friedman E Proc.International ASJC/SOC Conference, Santa Clara, USA, September 12—15, p335
[17] Wong S C, Lee G Y, Ma D J 2000 IEEE Transactions on Semiconductor Manufacturing 13 108
[18] Kim K K, Kim Y B 2009 IEEE Transactions on VLSI Systems 17 517
[19] Amelifard B, Fallah F, Pedram M 2008 IEEE Transactions on VLSI Systems 16 851
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[1] Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 (in Chinese) [王俊平、郝 跃 2009 58 4267]
[2] Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 (in Chinese) [李 鑫、Janet M Wang、唐卫清 2009 58 3603]
[3] Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 58 2631]
[4] Li X C, Mao J F, Huang H F, Liu Y 2005 IEEE Transactions on Electron Devices 52 2272
[5] Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[6] Banerjee K, Mehrotra A 2002 IEEE Transactions on Electron Devices 49 2001
[7] Naeemi A, Venkatesan R, Meindl J D 2004 IEEE Transactions on Electron Devices 51 980
[8] Mui M L, Banerjee K, Mehrotra A 2004 IEEE Transactions on Electron Devices 51 195
[9] Zhu Z M, Hao B T, Li R, Yang Y T 2010 Acta Phys. Sin. 59 1997 (in Chinese) [朱樟明、郝报田、李 儒、杨银堂 2010 59 1997]
[10] Ku J C, Ismail Y 2007 IEEE Transactions on VLSI Systems 15 963
[11] Zhu Z M, Zhong B, Hao B T, Yang Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明、钟 波、郝报田、杨银堂 2009 58 7124]
[12] Tam K H, Hu Y, He L 2008 IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27 1498
[13] Chang Y C, Tam K H, He L 2005 Proc. ISLPED, San Diego, USA, August 8—10, p137
[14] Diril A U, Dhillon Y S, Chatterjee A, Singh A D 2005 IEEE Transactions on VLSI Systems 13 1103
[15] Bakoglu H B, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990
[16] Chen G, Friedman E Proc.International ASJC/SOC Conference, Santa Clara, USA, September 12—15, p335
[17] Wong S C, Lee G Y, Ma D J 2000 IEEE Transactions on Semiconductor Manufacturing 13 108
[18] Kim K K, Kim Y B 2009 IEEE Transactions on VLSI Systems 17 517
[19] Amelifard B, Fallah F, Pedram M 2008 IEEE Transactions on VLSI Systems 16 851
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