Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

Dong Gang; Wu Wen-Shan; Yang Yin-Tang

doi:10.7498/aps.64.026601

Abstract

Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.

Keywords:

Authors and contacts

1.
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute, Xidian University, Xian 710071, China
Funds: Project supported by the National Natural Science Foundation of China (Grant No. 61334003).

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[5]	Liu W, Du H, Wang Y, Ma Y, Xie Y, Quan J, Yang H 2013 International Symposium on Quality Electronic Design Santa Clara, USA, March 4-6, 2013 p300
[6]	Wei S H, Lee Y M, Ho C T, Sun C T, Cheng L C 2013 International Symposium on VLSI Design, Automation and Test Hsinchu, China, April 22-24, 2013 p1
[7]	Kim J, Cho J, Pak J S, Song T 2010 International Conference on Electrical Performance of Electronic Packaging and Systems Austin, USA, October 25-27, 2010 p41
[8]	Zhao X, Lim S K 2010 Asia and South Pacific Design Automation Conference Taipei, China, January 18-21, 2010 p175
[9]	Sai M P D, Shang Y H, Tan C S, Lim S K 2013 IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 32 1734
[10]	Qian L B, Zhu Z M, Xia Y S, Ding R X, Yang Y T 2014 Chin. Phys. B 23 038402
[11]	Chen H T, Lin H L, Wang Z C, Hwang T T 2011 DATE Conference and Exhibition Grenoble, France, March 14-18, 2011 p1
[12]	Yang P, Chen H T, Hwang T T 2013 Asia and South Pacific Design Automation Conference Yokohama, Japan, January 22-25, 2013 p699
[13]	Zhao W S, Wang X P, Xu X L, Yin W Y 2010 Proc. IEEE Electrical Design of Advanced Packaging & Systems Symposium Singapore, December 7-9, 2010 p1
[14]	Chua T T, Ho S W, Li H Y, Khong C H, Liao E B, Chew S P, Lee W S, Lim L S, Pang X F, Kriangsak S L, Ng C, Nathapong S, Toh C H 2010 International Symposium on Quality Electronic Design Las Vegas, USA, June 1-4, 2010 p798
[15]	Han K J, Swaminathan M, Bandyopadhyay T 2010 IEEE Trans. Adv. Package 33 804
[16]	Todri A, Kundu S, Girard P, Bosio A, Dilillo L 2013 IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21 306
[17]	Savidis I, Friedman E G 2009 IEEE Trans. Electron Dev. 56 1873
[18]	Kim J, Pak J S, Cho J, Song E 2011 IEEE Trans. Compon. Packag. Manuf. Technol. 1 181
[19]	Hall S H, Hall G W, McCall J A 2000 High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (New York: John Wiley & Sons) p205
[20]	Liu E X, Li E P, Ewe W B, Lee H M 2011 IEEE Trans. Microw. Theory Tech. 59 1454
[21]	Katti G, Stucchi M, Meyer K D, Dehaene W 2010 IEEE Trans. Electron Dev. 57 256
[22]	Kim D Y, Kim J H, Pak J S, Lee H D, Lee J H, Park K W, Kim J H 2012 IEEE Electronic Components and Technology Conference California, USA, May 29-30, 2012 p1945
[23]	Elmiligi H, El-Kharashi M W, Gebali F 2013 Microprocess. Microsy. 37 530
[24]	Dong G, Yang Y, Chai C C, Yang Y T 2010 Chin. Phys. B 19 110202
[25]	Qian L B, Zhu Z M, Yang Y T 2012 Acta Phys. Sin. 61 068001 (in Chinese) [钱利波, 朱樟明, 杨银堂 2012 61 068001]
[26]	Savidis I, Alamc S M, Jain A, Pozder S, Jones R E, Chatterjee R 2010 Microelectron. J. 41 9
[27]	Zhu Z M, Zuo P, Yang Y T 2011 Acta Phys. Sin. 60 118001 (in Chinese) [朱樟明, 左平, 杨银堂 2011 60 118001]
[28]	Kim J, Cho J, Kim J, Yook J M, Kim J C, Lee J, Park K, Pak J S 2014 IEEE Trans. Compon. Packag. Manuf. Technol. 4 697
[29]	Greakis V, Avdikou C, Liolios A, Hatzopoulos A 2014 International Symposium on Design and Diagnostics of Electronic Circuits & Systems Warsaw, Poland, April 23-25, 2014 p310

Cited By

[1]	Lee Y J, Lim S K 2011 IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 30 1635
[2]	Zhao X, Minz J, Lim S K 2011 IEEE Trans. Compon. Packag. Manuf. Technol. 1 247
[3]	Zhu Z M, Wan D J, Yang Y T 2010 Acta Phys. Sin. 59 4837 (in Chinese) [朱樟明, 万达经, 杨银堂 2010 59 4837]
[4]	Khan N H, Alam S M, Hassoun S 2011 IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 19 647
[5]	Liu W, Du H, Wang Y, Ma Y, Xie Y, Quan J, Yang H 2013 International Symposium on Quality Electronic Design Santa Clara, USA, March 4-6, 2013 p300
[6]	Wei S H, Lee Y M, Ho C T, Sun C T, Cheng L C 2013 International Symposium on VLSI Design, Automation and Test Hsinchu, China, April 22-24, 2013 p1
[7]	Kim J, Cho J, Pak J S, Song T 2010 International Conference on Electrical Performance of Electronic Packaging and Systems Austin, USA, October 25-27, 2010 p41
[8]	Zhao X, Lim S K 2010 Asia and South Pacific Design Automation Conference Taipei, China, January 18-21, 2010 p175
[9]	Sai M P D, Shang Y H, Tan C S, Lim S K 2013 IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 32 1734
[10]	Qian L B, Zhu Z M, Xia Y S, Ding R X, Yang Y T 2014 Chin. Phys. B 23 038402
[11]	Chen H T, Lin H L, Wang Z C, Hwang T T 2011 DATE Conference and Exhibition Grenoble, France, March 14-18, 2011 p1
[12]	Yang P, Chen H T, Hwang T T 2013 Asia and South Pacific Design Automation Conference Yokohama, Japan, January 22-25, 2013 p699
[13]	Zhao W S, Wang X P, Xu X L, Yin W Y 2010 Proc. IEEE Electrical Design of Advanced Packaging & Systems Symposium Singapore, December 7-9, 2010 p1
[14]	Chua T T, Ho S W, Li H Y, Khong C H, Liao E B, Chew S P, Lee W S, Lim L S, Pang X F, Kriangsak S L, Ng C, Nathapong S, Toh C H 2010 International Symposium on Quality Electronic Design Las Vegas, USA, June 1-4, 2010 p798
[15]	Han K J, Swaminathan M, Bandyopadhyay T 2010 IEEE Trans. Adv. Package 33 804
[16]	Todri A, Kundu S, Girard P, Bosio A, Dilillo L 2013 IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21 306
[17]	Savidis I, Friedman E G 2009 IEEE Trans. Electron Dev. 56 1873
[18]	Kim J, Pak J S, Cho J, Song E 2011 IEEE Trans. Compon. Packag. Manuf. Technol. 1 181
[19]	Hall S H, Hall G W, McCall J A 2000 High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (New York: John Wiley & Sons) p205
[20]	Liu E X, Li E P, Ewe W B, Lee H M 2011 IEEE Trans. Microw. Theory Tech. 59 1454
[21]	Katti G, Stucchi M, Meyer K D, Dehaene W 2010 IEEE Trans. Electron Dev. 57 256
[22]	Kim D Y, Kim J H, Pak J S, Lee H D, Lee J H, Park K W, Kim J H 2012 IEEE Electronic Components and Technology Conference California, USA, May 29-30, 2012 p1945
[23]	Elmiligi H, El-Kharashi M W, Gebali F 2013 Microprocess. Microsy. 37 530
[24]	Dong G, Yang Y, Chai C C, Yang Y T 2010 Chin. Phys. B 19 110202
[25]	Qian L B, Zhu Z M, Yang Y T 2012 Acta Phys. Sin. 61 068001 (in Chinese) [钱利波, 朱樟明, 杨银堂 2012 61 068001]
[26]	Savidis I, Alamc S M, Jain A, Pozder S, Jones R E, Chatterjee R 2010 Microelectron. J. 41 9
[27]	Zhu Z M, Zuo P, Yang Y T 2011 Acta Phys. Sin. 60 118001 (in Chinese) [朱樟明, 左平, 杨银堂 2011 60 118001]
[28]	Kim J, Cho J, Kim J, Yook J M, Kim J C, Lee J, Park K, Pak J S 2014 IEEE Trans. Compon. Packag. Manuf. Technol. 4 697
[29]	Greakis V, Avdikou C, Liolios A, Hatzopoulos A 2014 International Symposium on Design and Diagnostics of Electronic Circuits & Systems Warsaw, Poland, April 23-25, 2014 p310

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Vol. 64, Issue 2 - 2015-01-20

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