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Optimization of interconnect power and repeater area is an important issue in the design of nanometer CMOS ICs. Based on RLC delay model, the paper proposes a new optimal model to minimize power and area overhead with constraints of target delay and target bandwidth. The proposed model is verified at 90 nm, 65 nm and 45 nm CMOS technology. Experimental result shows that the proposed model can save an average power consumption of 46% and 61% and can save an average area of 65% and 83% at the expense of 1/3 and 1/2 bandwidth, respectively. The proposed optimal model can be used in computer-aided design for nanometer CMOS system-on-chip.
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Keywords:
- nanometer interconnect power /
- repeater area /
- time delay /
- bandwidth
[1] ［2］Sylvester D, Keutzer K 1999 Proc. of Int. Symp. on Physical Design p193
[2] ［3］El-Moursy M A, Friedman E G 2007 Integration the VLSI Journal 40 461
[3] ［4］El-Moursy M A, Friedman E G 2005 Integration the VLSI Journal 38 205
[4] ［5］Karami M A, Afzali-kusha A 2006 Int. Conf. on Microelectronics p99
[5] ［6］lsmail Y I, Friedman E G 2000 IEEE Trans. on VLSI Systems 8 195
[6] ［7］Banerjee K, Mehrotra A 2002 IEEE Trans. on Electron Devices 49 2001
[7] ［8］Alpert C J, Devgan A, Fishburn J P 2001 IEEE Trans. Computer-Aided Design Integrated Circuits and Systems 20 90
[8] ［9］EI-Moursy M A 2003 13th ACM Great Lakes Symp. on VLSI p27［10］Tang M, Mao J F 2008 Int. Conf. on Microwave and Millimeter Wave Technology 2 479
[9] ］Hasani F, Masoumi N 2008 3th Int. Conf. on Design and technology of Integrated Systems in Nanoscale Era p1
[10] ］Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[11] ］Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 （in Chinese）［李鑫、 Janet M Wang、 唐卫清 2009 58 3603］
[12] ］Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 （in Chinese）［朱樟明、 钱利波、 杨银堂 2009 58 2631］
[13] ］Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 （in Chinese）［王俊平、 郝跃 2009 58 4267］
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[1] ［2］Sylvester D, Keutzer K 1999 Proc. of Int. Symp. on Physical Design p193
[2] ［3］El-Moursy M A, Friedman E G 2007 Integration the VLSI Journal 40 461
[3] ［4］El-Moursy M A, Friedman E G 2005 Integration the VLSI Journal 38 205
[4] ［5］Karami M A, Afzali-kusha A 2006 Int. Conf. on Microelectronics p99
[5] ［6］lsmail Y I, Friedman E G 2000 IEEE Trans. on VLSI Systems 8 195
[6] ［7］Banerjee K, Mehrotra A 2002 IEEE Trans. on Electron Devices 49 2001
[7] ［8］Alpert C J, Devgan A, Fishburn J P 2001 IEEE Trans. Computer-Aided Design Integrated Circuits and Systems 20 90
[8] ［9］EI-Moursy M A 2003 13th ACM Great Lakes Symp. on VLSI p27［10］Tang M, Mao J F 2008 Int. Conf. on Microwave and Millimeter Wave Technology 2 479
[9] ］Hasani F, Masoumi N 2008 3th Int. Conf. on Design and technology of Integrated Systems in Nanoscale Era p1
[10] ］Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[11] ］Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 （in Chinese）［李鑫、 Janet M Wang、 唐卫清 2009 58 3603］
[12] ］Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 （in Chinese）［朱樟明、 钱利波、 杨银堂 2009 58 2631］
[13] ］Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 （in Chinese）［王俊平、 郝跃 2009 58 4267］
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