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In this paper,based on the research of the features about high voltage and high current under electrostatic discharge(ESD),the new 3D model of 0.6 μm gate-grounded NMOS(ggNMOS) ESD protection circuit with CSMC 6S06DPDM-CT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model; systematic study about the effect of drain contact to gate spacing(DCGS)and the source contact to gate spacing(SCGS)on the relative protection circuit robustness index(turn-on voltage,breakdown voltage,self-heating peak,etc)have been done based on this model. The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the self-heating peak value of protection circuit. To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously. Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent. The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.
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Keywords:
- gate grounded NMOS(ggNMOS) /
- electrostatic discharge(ESD) /
- drain contact to gate spacing(DCGS) /
- source contact to gate spacing(SCGS)
[1] Ameraskera A,Duvvury C 2002 ESD in silicon integrated circuits (2nd ed) (New York:John Wiley and Sons) p56
[2] A B Ai M,Bai S,Hali M 2008 Chin. Phys. B 57 1161
[3] Fichtner W,Esmark K,Stadler W Electron Devices Meeting IEDM Washington,D.C.,USA,Dec. 3—5,2001 p14
[4] Xie H L,Zhan R Y,Albert W 2004 Proceedings of the Fifth IEEE International Caracas Conference on Device,Circuits and Systems Punta Cana,Dominican Republic,Nov. 3—5,2004 p61
[5] Steven H V,Gross V 1993 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Lake Buena Vista,FL,USA,1993 p251
[6] Fang J P,Hao Y,Liu H X,Zhang J F,Zhu Z W 2006 Acta Phys. Sin. 55 5878 (in Chinese) [方建平、郝 跃、刘红侠、张金凤、朱志炜 2006 55 5878]
[7] Steven H V 2006 ESD Circuits And Devices (New York:John Wiley and Sons) p82
[8] Integrated Systems Engineering Corp. 2005 ISE-TCAD Dessis Simulation Users Manual Zurich,Switzerland,2005 p55
[9] Selberher S 1984 Analysis and Simulation of Semiconductor Device (Berlin:Springer-Verlag) p72
[10] Ma W,Hao Y 2003 Chinese Journal of Semiconductors 24 892 (in Chinese) [马 巍、郝 跃 2003 半导体学报 24 892]
[11] Duan X R,Tan C H,Wang Y G,Xu M Z 2005 Acta Phys. Sin. 54 3884 (in Chinese) [段小蓉、谭长华、王彦刚、许铭真 2005 54 3884]
[12] Pimbley J M,Cumberbatch E,Hagan P S 1987 IEEE Trans. Electron Device p834
[13] Varahramyan K,Verret E J 1996 Solid-State Electronic 39 1601
[14] Cao Y R,Hao Y,Liu H X,Ma X H,Zhu Z W 2007 Acta Phys. Sin. 56 1075 (in Chinese) [曹艳荣、郝 跃、刘红侠、马晓华、朱志炜 2007 56 1075]
[15] Russ C C,Mergens M P J,Verhagel K G 2001 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Sympo-sium Oregon,Portland,Sept. 11—13,2001 p22
[16] Mergens M P,Russ C C,Armer J Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Oregon ,Portland,Sept. 11-13,2001 p11
[17] Jia R X,Liu H X,Luan S Z 2008 Acta Phys. Sin. 57 2524 (in Chinese) [贾仁需、刘红侠、栾苏珍 2008 57 2524]
[18] Jiang Y X,Li J,Ran F 2009 Chinese Journal of Semiconductors 30 084007 (in Chinese) [姜玉稀、李 娇、冉 峰 2009 半导体学报 30 084007]
[19] Lee J C,Hoque M A 2000 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Anaheim,USA,Sept. 26—28,2000 p97
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[1] Ameraskera A,Duvvury C 2002 ESD in silicon integrated circuits (2nd ed) (New York:John Wiley and Sons) p56
[2] A B Ai M,Bai S,Hali M 2008 Chin. Phys. B 57 1161
[3] Fichtner W,Esmark K,Stadler W Electron Devices Meeting IEDM Washington,D.C.,USA,Dec. 3—5,2001 p14
[4] Xie H L,Zhan R Y,Albert W 2004 Proceedings of the Fifth IEEE International Caracas Conference on Device,Circuits and Systems Punta Cana,Dominican Republic,Nov. 3—5,2004 p61
[5] Steven H V,Gross V 1993 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Lake Buena Vista,FL,USA,1993 p251
[6] Fang J P,Hao Y,Liu H X,Zhang J F,Zhu Z W 2006 Acta Phys. Sin. 55 5878 (in Chinese) [方建平、郝 跃、刘红侠、张金凤、朱志炜 2006 55 5878]
[7] Steven H V 2006 ESD Circuits And Devices (New York:John Wiley and Sons) p82
[8] Integrated Systems Engineering Corp. 2005 ISE-TCAD Dessis Simulation Users Manual Zurich,Switzerland,2005 p55
[9] Selberher S 1984 Analysis and Simulation of Semiconductor Device (Berlin:Springer-Verlag) p72
[10] Ma W,Hao Y 2003 Chinese Journal of Semiconductors 24 892 (in Chinese) [马 巍、郝 跃 2003 半导体学报 24 892]
[11] Duan X R,Tan C H,Wang Y G,Xu M Z 2005 Acta Phys. Sin. 54 3884 (in Chinese) [段小蓉、谭长华、王彦刚、许铭真 2005 54 3884]
[12] Pimbley J M,Cumberbatch E,Hagan P S 1987 IEEE Trans. Electron Device p834
[13] Varahramyan K,Verret E J 1996 Solid-State Electronic 39 1601
[14] Cao Y R,Hao Y,Liu H X,Ma X H,Zhu Z W 2007 Acta Phys. Sin. 56 1075 (in Chinese) [曹艳荣、郝 跃、刘红侠、马晓华、朱志炜 2007 56 1075]
[15] Russ C C,Mergens M P J,Verhagel K G 2001 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Sympo-sium Oregon,Portland,Sept. 11—13,2001 p22
[16] Mergens M P,Russ C C,Armer J Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Oregon ,Portland,Sept. 11-13,2001 p11
[17] Jia R X,Liu H X,Luan S Z 2008 Acta Phys. Sin. 57 2524 (in Chinese) [贾仁需、刘红侠、栾苏珍 2008 57 2524]
[18] Jiang Y X,Li J,Ran F 2009 Chinese Journal of Semiconductors 30 084007 (in Chinese) [姜玉稀、李 娇、冉 峰 2009 半导体学报 30 084007]
[19] Lee J C,Hoque M A 2000 Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium Anaheim,USA,Sept. 26—28,2000 p97
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