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随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一. 由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一. 但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤. 此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战. 本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理. 在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.
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关键词:
- 隧道场效应晶体管(TFET) /
- 静电放电(ESD) /
- 传输线脉冲(TLP) /
- 带带隧穿机理
Power consumption has been the major bottleneck in the development of integrated circuits with reduced critical dimensions and improved integrated level. Tunnel field effect transistor (TFET) has been investigated as one of the promising replacements for traditional metal oxide semiconductor field effect transistor (MOSFET), owing to the introduction of band to band tunneling (BTBT) mechanism based on which a smaller subthreshold slope is achieved. However, a thinner oxide layer and a shorter channel length in TFET may induce localization of high current density, high electrical field distribution, and generation of heat, which abate the probability to survive electrostatic discharge (ESD). Besides, the novel BTBT operating principles also present a challenge to TFET ESD protection design. In this paper transmission line pulse test method is adopted to analyze the working principle of conventional TFET at onset, holding, discharge, and second breakdown during an ESD event. Based on these a new TFET ESD device protection design is proposed and characterized with a deeply doped n+ pocket near the source region beneath the gate, which can make effective adjustments of contact potential barrier, reduce tunneling junction width, thus better ESD design windows are obtained.-
Keywords:
- tunnel field Effect transistor (TFET) /
- electrostatic discharge (ESD) /
- transmission line pulse (TLP) /
- band-to-band tunneling
[1] Wang P F, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M, Schmitt-Landsiedel D, Hansch W 2004 Solid State Electron. 48 2281
[2] Bhuwalka K K, Schulze J, Eisele I 2004 Jpn. J. Appl. Phys. 43 4073
[3] [4] [5] Appenzeller J, Lin Y M, Knoch J, Avouris Ph 2004 Phys. Rev. Lett. 93 196805
[6] Uenmura T, Baba T 1996 Jpn. J. Appl. Phys. 35 1668
[7] [8] Choi W Y, Park B G, Lee J. D, Liu T J K 2007 IEEE Electron Dev. Lett. 28 743
[9] [10] [11] Mantl S, Knoll L, Schmidt M, Richter S, Nichau A, Trellenkamp S, Schafer A, Wirths S, Blaeser S, Buca D, Zhao Q T 2013 14^ International Conference on Ultimate Integration on Silicon (ULIS) Coventry, United Kingdom, March 19-21, 2013, p15
[12] Wang Y, Jia S, Sun L, Zhang G G, Zhang X, Ji L 2007 Acta Phys. Sin. 56 7242 (in Chinese)[王源, 贾嵩, 孙磊, 张钢刚, 张兴 2007 56 7242]
[13] [14] [15] Wang A Z 2002 On-chip ESD protection for integrated circuits: an IC design perspective (Boston: Kluwer Academic) p2-7
[16] [17] Woo R 2009 Ph. D. Dissertation (California: Stanford University)
[18] Russ C 2008 Microelectron. Reliab. 48 1403
[19] [20] [21] Kane E O 1961 J Appl Phys 32 83
[22] [23] Hurkx G A M, Klaassen D B M, Knuvers M P G 1992 IEEE Tran. Electron Dev. 39 331
[24] Schenk A 1993 Solid State Electron. 36 19
[25] [26] [27] Biswas A, Dan S S, Royer C L, Grabinski W, Ionescu A M 2012 Microelectron. Eng. 98 334
[28] Shen C, Yang L T, Samudra G, Yeo Y C 2011 Solid State Electron. 57 23
[29] [30] Jiao Y P, Wei K L, Wang T H, Du G, Liu X Y 2013 J. Semiconductor. 34 092002
[31] [32] [33] Synopsys Corp 2010 Sentaurus Device User Guide. Ver. E-201012
[34] Wu X P, Yang Y T, Gao H X, Dong G, Chai C C 2013 Acta Phys. Sin. 62 047203 (in Chinese)[吴晓鹏, 杨银堂, 高海霞, 董刚, 柴常春 2013 62 047203]
[35] [36] [37] Zhang B, Chai C C, Yang Y T 2010 Acta Phys. Sin. 59 8063 (in Chinese)[张冰, 柴常春, 杨银堂 2010 59 8063]
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[1] Wang P F, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M, Schmitt-Landsiedel D, Hansch W 2004 Solid State Electron. 48 2281
[2] Bhuwalka K K, Schulze J, Eisele I 2004 Jpn. J. Appl. Phys. 43 4073
[3] [4] [5] Appenzeller J, Lin Y M, Knoch J, Avouris Ph 2004 Phys. Rev. Lett. 93 196805
[6] Uenmura T, Baba T 1996 Jpn. J. Appl. Phys. 35 1668
[7] [8] Choi W Y, Park B G, Lee J. D, Liu T J K 2007 IEEE Electron Dev. Lett. 28 743
[9] [10] [11] Mantl S, Knoll L, Schmidt M, Richter S, Nichau A, Trellenkamp S, Schafer A, Wirths S, Blaeser S, Buca D, Zhao Q T 2013 14^ International Conference on Ultimate Integration on Silicon (ULIS) Coventry, United Kingdom, March 19-21, 2013, p15
[12] Wang Y, Jia S, Sun L, Zhang G G, Zhang X, Ji L 2007 Acta Phys. Sin. 56 7242 (in Chinese)[王源, 贾嵩, 孙磊, 张钢刚, 张兴 2007 56 7242]
[13] [14] [15] Wang A Z 2002 On-chip ESD protection for integrated circuits: an IC design perspective (Boston: Kluwer Academic) p2-7
[16] [17] Woo R 2009 Ph. D. Dissertation (California: Stanford University)
[18] Russ C 2008 Microelectron. Reliab. 48 1403
[19] [20] [21] Kane E O 1961 J Appl Phys 32 83
[22] [23] Hurkx G A M, Klaassen D B M, Knuvers M P G 1992 IEEE Tran. Electron Dev. 39 331
[24] Schenk A 1993 Solid State Electron. 36 19
[25] [26] [27] Biswas A, Dan S S, Royer C L, Grabinski W, Ionescu A M 2012 Microelectron. Eng. 98 334
[28] Shen C, Yang L T, Samudra G, Yeo Y C 2011 Solid State Electron. 57 23
[29] [30] Jiao Y P, Wei K L, Wang T H, Du G, Liu X Y 2013 J. Semiconductor. 34 092002
[31] [32] [33] Synopsys Corp 2010 Sentaurus Device User Guide. Ver. E-201012
[34] Wu X P, Yang Y T, Gao H X, Dong G, Chai C C 2013 Acta Phys. Sin. 62 047203 (in Chinese)[吴晓鹏, 杨银堂, 高海霞, 董刚, 柴常春 2013 62 047203]
[35] [36] [37] Zhang B, Chai C C, Yang Y T 2010 Acta Phys. Sin. 59 8063 (in Chinese)[张冰, 柴常春, 杨银堂 2010 59 8063]
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