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微互连铜柱凸点因其密度高、导电性好、噪声小被广泛应用于存储芯片、高性能计算芯片等封装领域,研究铜柱凸点界面行为对明确其失效机理和组织演变规律、提升倒装封装可靠性具有重要意义.采用热电应力实验、在线电学监测、红外热像测试和微观组织分析等方法,研究Cu/Ni/SnAg1.8/Cu微互连倒装铜凸点在温度100150 ℃、电流密度21043104 A/cm2热电应力下的互连界面行为、寿命分布、失效机理及其影响因素.铜柱凸点在热电应力下的界面行为可分为Cu6Sn5生长和Sn焊料消耗、Cu6Sn5转化成Cu3Sn、空洞形成及裂纹扩展3个阶段,Cu6Sn5转化为Cu3Sn的速率与电流密度正相关.热电应力下,铜凸点互连存在Cu焊盘消耗、焊料完全合金化成Cu3Sn、阴极镍镀层侵蚀和层状空洞4种失效模式.基板侧Cu焊盘和铜柱侧Ni镀层的溶解消耗具有极性效应,当Cu焊盘位于阴极时,电迁移方向与热迁移方向相同,加速Cu焊盘的溶解以及Cu3Sn生长,当Ni层为阴极时,电迁移促进Ni层的消耗,在150 ℃,2.5104 A/cm2下经历2.5 h后,Ni阻挡层出现溃口,导致Ni层一侧的铜柱基材迅速转化成(Cux,Niy)6Sn5和Cu3Sn合金.铜柱凸点互连寿命较好地服从2参数威布尔分布,形状参数为7.78,为典型的累积耗损失效特征.研究结果表明:相比单一高温应力,热电综合应力显著加速并改变了铜柱互连界面金属间化合物的生长行为和失效机制.Micro-interconnection copper pillar bumps are being widely used in the packaging areas of memory chip and high performance computer due to their high density, good conductivity and low noise. Studying the interfacial behavior of copper pillar bump is of great significance for understanding its failure mechanism and microstructure evolution in order to improve the reliability of flip chip package. The thermoelectric stress test, in-situ monitor, infrared thermography test, and microstructure analysis method are employed to study the interfacial reaction, life distribution, failure mechanism and their effect factors of Cu/Ni/SnAg1.8/Cu flip chip copper pillar interconnects under 9 groups of thermoelectric stresses including 2104-3104 A/cm2 and 100-150℃. Under thermoelectric stresses, the interfacial reaction of Cu pillar can be divided into three stages:Cu6Sn5 growth and Sn solder exhaustion; the Cu6Sn5 phase transformation, exhaustion and the Cu3Sn phase growth; voids formation and crack propagation. The rate of Cu6Sn5 phase transforming into Cu3Sn phase is positively correlated with the current density. There are four kinds of failure modes including Cu pad consumption, solder complete consumption and transformation into Cu3Sn, Ni plating layer erosion and strip voids. An obvious polar effect is observed during the dissolution of Cu pads on the substrate side and the Ni layer on the Cu pillar side. When Cu pad is located at the cathode, the direction of electron flow is the same as that of the heat flow, and it can accelerate the consumption of Cu pad and the growth of Cu3Sn. When Ni layer serves as the cathode, the electron flow can enhance the consumption of Ni layer. Under 150℃ and 2.5104 A/cm2, the local Ni barrier layer is eroded after 2.5 h, which results in the transformation of Cu pillar on the Ni side into (Cux, Niy)6Sn5 and Cu3Sn alloy. The life of Cu pillar interconnection complies well to the 2-parameter Weibull distribution with a shape parameter of 7.78, which is a typical characteristic of cumulative wear-out failure. The results show that the intermitallic growth behavior and failure mechanism at Cu pillar interconnects are significantly accelerated and changed under thermoelectric stresses compared with the scenario under the single high temperature stress.
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Keywords:
- Cu pillar bump /
- interfacial reaction /
- failure mechanism /
- thermoelectric stress
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[12] Frear D R, Burchett S N, Morgan H S 1994 The Mechanics of Solder Alloy Interconnects (New York: van Nostrand Reinold) pp58-61
[13] Chen L D, Huang M L, Zhou S M, Ye S, Ye Y M, Wang J F, Cao X 2011 Proceeding of the International Electronic Packaging Technology High Density Packaging Shanghai, August 8-11, 2011 p316
[14] Kim B J, Lim G T, Kim J, Lee K W 2009 Met. Mater. Int. 15 815
[15] Ho P S, Kwok T 1989 Rep. Prog. Phys. 52 301
[16] Huang M L, Chen L D, Zhou S M, Zhao N 2012 Acta Phys. Sin. 61 198104 (in Chinese)[黄明亮, 陈雷达, 周少明, 赵宁 2012 61 198104]
[17] Jeong M H, Kim J W, Kwak B H, Park Y B 2012 Microelectr. Engineer. 89 50
[18] Hsiao Y H, Lin K L, Lee C W, Shao Y H, Lai Y S 2012 J. Electron. Mater. 41 3368
[19] Meinshausen L, Fremont H, Weidezaage K, Plano B 2015 Microelectr. Reliab. 55 192
[20] Gu X, Chan Y C 2009 J. Appl. Phys. 105 093537
[21] Song J Y, Yu J, Lee T Y 2004 Scripta Mater. 51 167
[22] An R, Tian Y H, Zhang R, Wang C Q 2015 J. Mater. Electron. 26 2674
[23] Sequeira C A C, Amaral L 2014 Trans. Nonferr. Metals Soc. China 24 1
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[1] Ding M, Wang G, Chao P, Ho P S, Su P, Uehling T 2006 J. Appl. Phys. 99 094906
[2] Kwak B H, Jeong M H, Park Y B 2013 Jpn. J. Appl. Phys. 51 361
[3] Tu K N 2003 J. Appl. Phys. 94 5451
[4] Kim B J, Lim G T, Kim J 2010 J. Electron. Mater. 39 2281
[5] Jeong M H, Kim J W, Kwak B H, Kim B J, Lee K W, Kim J D 2011 Korean J. Met. Mater. 49 180
[6] Kim B J, Lim G T, Kim J D, Lee K W, Park Y B, Lee H Y, Joo Y C 2010 J. Electron. Mater. 39 2281
[7] Chandra Rao B S S, Kripesh V, Zeng K Y 2011 61st Electronic Components and Technology Conference Lake Buena Vista, May 31-3 June, 2011 p100
[8] Ma H C, Guo J D, Chen J Q 2015 J. Mater. Sci.: Mater. Electron. 26 7690
[9] Lai Y S, Chiu Y T, Chen J 2008 J. Electron. Mater. 37 1624
[10] Hsiao H Y, Trigg A D, Chai T C 2015 IEEE Trans. Compon. Packag. Manufact. Technol. 5 314
[11] Li Y 2010 M. S. Dissertation (Chengdou: University of Electronic Science and Technology of China) (in Chinese)[李艳 2010 硕士学位论文(成都: 电子科技大学)]
[12] Frear D R, Burchett S N, Morgan H S 1994 The Mechanics of Solder Alloy Interconnects (New York: van Nostrand Reinold) pp58-61
[13] Chen L D, Huang M L, Zhou S M, Ye S, Ye Y M, Wang J F, Cao X 2011 Proceeding of the International Electronic Packaging Technology High Density Packaging Shanghai, August 8-11, 2011 p316
[14] Kim B J, Lim G T, Kim J, Lee K W 2009 Met. Mater. Int. 15 815
[15] Ho P S, Kwok T 1989 Rep. Prog. Phys. 52 301
[16] Huang M L, Chen L D, Zhou S M, Zhao N 2012 Acta Phys. Sin. 61 198104 (in Chinese)[黄明亮, 陈雷达, 周少明, 赵宁 2012 61 198104]
[17] Jeong M H, Kim J W, Kwak B H, Park Y B 2012 Microelectr. Engineer. 89 50
[18] Hsiao Y H, Lin K L, Lee C W, Shao Y H, Lai Y S 2012 J. Electron. Mater. 41 3368
[19] Meinshausen L, Fremont H, Weidezaage K, Plano B 2015 Microelectr. Reliab. 55 192
[20] Gu X, Chan Y C 2009 J. Appl. Phys. 105 093537
[21] Song J Y, Yu J, Lee T Y 2004 Scripta Mater. 51 167
[22] An R, Tian Y H, Zhang R, Wang C Q 2015 J. Mater. Electron. 26 2674
[23] Sequeira C A C, Amaral L 2014 Trans. Nonferr. Metals Soc. China 24 1
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