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The probability models of 2 different quantum cellular automaton (QCA) adders are based on the theory of probabilistic transfer matrix and circuit partition. The effect of individual component on the overall fault-tolerance is fully analyzed at the same level. The simulation shows that the effect of the wire is minor when the success probability is low, while the overall fault-tolerance rises sharply once the success probability is high. And the inverter is considered to be a major factor that affects the overall fault-tolerance in the variation range of parameter. Frobenbius norm of the overall error probabilistic transfer matrix is employed to study the fault-tolerance difference. The result shows that the overall fault-tolerance of QCA adder consisting of 5-input majority is superior to the other. Such fault-tolerance analyses should be used for a better characterization of QCA circuit design and fault-tolerance improvement.
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Keywords:
- probabilistic transfer matrix /
- adder /
- fault-tolerance /
- Frobenius norm
[1] Lent C S, Tougaw P D, Porod W, Bernstein G H 1993 Nanotechnology 4 49
[2] Tougaw P D, Lent C S 1994 Appl. Phys. 75 1818
[3] Azghadi M R, Kavehei O, Navi K 2007 J. Appl. Sci. 7 3460
[4] Navi K, Farazkish R, Sayedsalehi S, Azghadi M R 2010 Microelectron. J. 41 820
[5] Zhang R M, Walus K, Wang W, Jullien G A 2004 IEEE Trans. Nanotechnol. 3 443
[6] Cho H, Swartzlander E E 2007 IEEE Symposium on Computer Arithmetic Montpellier, France, June 25-27, 2007 p7
[7] Xia Y S, Qiu K M 2009 J. Electroni. Inform. Technol. 31 1517 (in Chinese) [夏银水, 裘科名 2009 电子与信息学报 31 1517]
[8] Tahoori M B, Momenzadeh M, Huang J, Lombardi F 2004 Proceedings of the 22nd IEEE VLSI Test Symposium 2004 Boston, April 25-29, 2004 p291
[9] Dysart T J, Kogge P M 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems 2008 p72
[10] Wei T Q, Wu K J, Karri R Orailoglu A 2005 IEEE 2005 p1192
[11] Bhaduri D, Shukla S, Graham P, Gokhale M 2007 IEEE Trans. Nanotechno. 6 265
[12] Patel K N, Markov I L, Hayes J P 2003 Proc. Int. Workshop Logic Synthesis (IWLS'03), 2003 p59
[13] Krishnaswamy S, Viamontes G F, Markov I L, Hayes J P 2005 Proceedings of the Conference on Design, Automation and Test in Europe Washington DC, 2005 p282
[14] Bahar R I, Frohm E A, Gaona C M, Hachtel G D, Macii E, Pardo A, Somenzi F 1997 Formal Methods in System Design 10 171
[15] Chen J, Li H 2006 Proceedings of 2006 IEEE International Symposium on Circuits and Systems, Kos, 2006 p3522
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[1] Lent C S, Tougaw P D, Porod W, Bernstein G H 1993 Nanotechnology 4 49
[2] Tougaw P D, Lent C S 1994 Appl. Phys. 75 1818
[3] Azghadi M R, Kavehei O, Navi K 2007 J. Appl. Sci. 7 3460
[4] Navi K, Farazkish R, Sayedsalehi S, Azghadi M R 2010 Microelectron. J. 41 820
[5] Zhang R M, Walus K, Wang W, Jullien G A 2004 IEEE Trans. Nanotechnol. 3 443
[6] Cho H, Swartzlander E E 2007 IEEE Symposium on Computer Arithmetic Montpellier, France, June 25-27, 2007 p7
[7] Xia Y S, Qiu K M 2009 J. Electroni. Inform. Technol. 31 1517 (in Chinese) [夏银水, 裘科名 2009 电子与信息学报 31 1517]
[8] Tahoori M B, Momenzadeh M, Huang J, Lombardi F 2004 Proceedings of the 22nd IEEE VLSI Test Symposium 2004 Boston, April 25-29, 2004 p291
[9] Dysart T J, Kogge P M 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems 2008 p72
[10] Wei T Q, Wu K J, Karri R Orailoglu A 2005 IEEE 2005 p1192
[11] Bhaduri D, Shukla S, Graham P, Gokhale M 2007 IEEE Trans. Nanotechno. 6 265
[12] Patel K N, Markov I L, Hayes J P 2003 Proc. Int. Workshop Logic Synthesis (IWLS'03), 2003 p59
[13] Krishnaswamy S, Viamontes G F, Markov I L, Hayes J P 2005 Proceedings of the Conference on Design, Automation and Test in Europe Washington DC, 2005 p282
[14] Bahar R I, Frohm E A, Gaona C M, Hachtel G D, Macii E, Pardo A, Somenzi F 1997 Formal Methods in System Design 10 171
[15] Chen J, Li H 2006 Proceedings of 2006 IEEE International Symposium on Circuits and Systems, Kos, 2006 p3522
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