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为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.
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关键词:
- 横向双扩散金属氧化物半导体器件 /
- 超级结 /
- 比导通电阻 /
- P型覆盖层
In order to design the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with low loss required for a power integrated circuit, a new super junction LDMOS with the P covered layer which is based on the existing N buffered super junction LDMOS is proposed in this paper for the first time. The key feature of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer, which is different from the N buffered super junction LDMOS. In this structure, the specific on-resistance of the device is reduced by using the high doped super junction layer; the problem of the substrate-assisted depletion which is produced due to the P-type substrate of the N-channel super junction LDMOS is eliminated by completely compensating for the charges of the N-type buffered layer and the P-type covered layer, thus improving the breakdown voltage. The charges of the N-type and P-type pillars are depleted completely. A new transmission path at the on-state is formed by N buffered layer to reduce the specific on-resistance, which is similar to the N buffered super junction LDMOS. However, the effect of N-type buffered layer of N buffered super junction LDMOS is not fully used. The drift region of the device is further optimized by the proposed device to reduce the specific on-resistance. The charge concentration of the N-type buffered layer in the proposed device is improved by the effect of charge compensation of the P covered layer. It is clear that high breakdown voltage and low specific on-resistance are realized in the proposed device by introducing the P-type covered layer and the N-type buffered layer. The results of the 3 D-ISE software suggest that when the drift region is on a scale of 10 μm, a specific on-resistance of 4.26 mΩ·cm2 obtained from P covered super junction LDMOS by introducing P covered layer and N buffered layer is reduced by about 59% compared with that of conventional super junction LDMOS which is 10.47 mΩ·cm2, and reduced by about 43% compared with that of N Buffered super junction LDMOS which is 7.46 mΩ·cm2.-
Keywords:
- lateral double-diffused metal-oxide-semiconductor field-effect transistor /
- super junction /
- specific on resistance /
- P covered layer
[1] He Y D, Zhang G G, Zhang X 2014 Proceedings of the 17th International Power Semiconductor Devices and ICs Waikoloa, USA, June 15-19, 2014 p171
[2] Kyungho L, Haeung J, Byunghee C, Joonhee C, Pang Y S, Jinwoo M, Susanna K 2013 Proceedings of the 25th International Power Semiconductor Devices and ICs Kanazawa, May 26-30, 2013 p163
[3] Chen X B, Wang X, Johnny K O S 2000 IEEE Trans. Electron Dev. 47 1280
[4] Chen X B, Johnny K O S 2001 IEEE Trans. Electron Dev. 48 344
[5] Sameh G, Khalil N, Salama C A T 2003 IEEE Trans. Electron Dev. 50 1385
[6] Sameh G, Khalil N, Li Z H, Salama C A T 2004 IEEE Trans. Electron Dev. 51 1185
[7] Duan B X, Zhang B, Li Z J 2007 Chin. J. Semicond. 28 166
[8] Park Y, Salama C T 2005 Proceedings of the 17th International Power Semiconductor Devices and ICs SantaBarbara, USA, May 26-30, 2005 p163
[9] Zhang B, Chen L, Wu J, Li Z J 2005 International Conference on Communications, Circuits and System Hongkong, May 27-30, 2005 p1399
[10] Wu W, Zhang B, Fang J, Luo X R, Li Z J 2013 Chin. Phys. B 22 068501
[11] Duan B X, Yang Y T, Zhang B 2009 IEEE Electron Dev. Lett. 30 305
[12] Duan B X, Yang Y T 2011 Micro. Nano Lett. 6 881
[13] Duan B X, Cao Z, Yuan S, Yuan X N, Yang Y T 2014 Acta Phys. Sin. 63 247301 (in Chinese) [段宝兴, 曹震, 袁嵩, 袁小宁, 杨银堂 2014 63 247301]
[14] Duan B X, Cao Z, Yuan X N, Yang Y T 2014 Acta Phys. Sin. 63 227302 (in Chinese) [段宝兴, 曹震, 袁小宁, 杨银堂 2014 63 227302]
[15] Michael A, Vladimir R 1985 International Electron Devices Meeting Washington, USA, December 1-4, 1985 p736
[16] ISE TCAD Manuals, Release 10.0, Synopsys Co., Switzerland
[17] Park I Y, Choi Y K, Ko K Y, Yoon C J, Kim Y S, Kim M Y, Kim H T, Lim H C, Kim N J, Yoo K D 2009 Proceedingsof the 21th International Power Semiconductor Devices and ICs Barcelona, Spain, June 15-17, 2009 p192
[18] Chen W J, Zhang B, Li Z J 2007 Chin. J. Semicond. 28 365
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[1] He Y D, Zhang G G, Zhang X 2014 Proceedings of the 17th International Power Semiconductor Devices and ICs Waikoloa, USA, June 15-19, 2014 p171
[2] Kyungho L, Haeung J, Byunghee C, Joonhee C, Pang Y S, Jinwoo M, Susanna K 2013 Proceedings of the 25th International Power Semiconductor Devices and ICs Kanazawa, May 26-30, 2013 p163
[3] Chen X B, Wang X, Johnny K O S 2000 IEEE Trans. Electron Dev. 47 1280
[4] Chen X B, Johnny K O S 2001 IEEE Trans. Electron Dev. 48 344
[5] Sameh G, Khalil N, Salama C A T 2003 IEEE Trans. Electron Dev. 50 1385
[6] Sameh G, Khalil N, Li Z H, Salama C A T 2004 IEEE Trans. Electron Dev. 51 1185
[7] Duan B X, Zhang B, Li Z J 2007 Chin. J. Semicond. 28 166
[8] Park Y, Salama C T 2005 Proceedings of the 17th International Power Semiconductor Devices and ICs SantaBarbara, USA, May 26-30, 2005 p163
[9] Zhang B, Chen L, Wu J, Li Z J 2005 International Conference on Communications, Circuits and System Hongkong, May 27-30, 2005 p1399
[10] Wu W, Zhang B, Fang J, Luo X R, Li Z J 2013 Chin. Phys. B 22 068501
[11] Duan B X, Yang Y T, Zhang B 2009 IEEE Electron Dev. Lett. 30 305
[12] Duan B X, Yang Y T 2011 Micro. Nano Lett. 6 881
[13] Duan B X, Cao Z, Yuan S, Yuan X N, Yang Y T 2014 Acta Phys. Sin. 63 247301 (in Chinese) [段宝兴, 曹震, 袁嵩, 袁小宁, 杨银堂 2014 63 247301]
[14] Duan B X, Cao Z, Yuan X N, Yang Y T 2014 Acta Phys. Sin. 63 227302 (in Chinese) [段宝兴, 曹震, 袁小宁, 杨银堂 2014 63 227302]
[15] Michael A, Vladimir R 1985 International Electron Devices Meeting Washington, USA, December 1-4, 1985 p736
[16] ISE TCAD Manuals, Release 10.0, Synopsys Co., Switzerland
[17] Park I Y, Choi Y K, Ko K Y, Yoon C J, Kim Y S, Kim M Y, Kim H T, Lim H C, Kim N J, Yoo K D 2009 Proceedingsof the 21th International Power Semiconductor Devices and ICs Barcelona, Spain, June 15-17, 2009 p192
[18] Chen W J, Zhang B, Li Z J 2007 Chin. J. Semicond. 28 365
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