With the continuous downscaling of CMOS technology, process-induced mechanical stress effects become remarkable with the shrinkage of active region. Many processing steps individually or collectively contribute to mechanical stress development. The stress results in not only the layout dependency of device performances, but also diverse reliability issues, which would shorten the chip lifetime. In many cases, stress-related problems are determinative of IC yield. Here, based on the summary of mechanical stress sources, we review the achievements to date in observing and understanding these stress problems, and propose the prospective considerations when analyzing stress-related phenomenon.