基于青藏高原的14 nm FinFET和28 nm平面CMOS工艺SRAM单粒子效应实时测量试验

张战刚; 杨少华; 林倩; 雷志锋; 彭超; 何玉娟

doi:10.7498/aps.72.20230161

摘要

本文基于海拔为4300 m的拉萨羊八井国际宇宙射线观测站, 开展了14 nm FinFET和28 nm平面互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)工艺静态随机存取存储器(static random-access memory, SRAM)阵列的大气辐射长期实时测量试验. 试验持续时间为6651 h, 共观测到单粒子翻转(single event upset, SEU)事件56个, 其中单位翻转(single bit upset, SBU) 24个, 多单元翻转(multiple cell upset, MCU) 32个. 结合之前开展的65 nm工艺SRAM结果, 研究发现, 随着工艺尺寸的减小, 器件的整体软错误率(soft error rate, SER)持续降低. 但是, 相比于65和14 nm工艺器件, 28 nm工艺器件的MCU SER最大, 其MCU占比(57%)超过SBU, MCU最大位数为16位. 虽然14 nm FinFET器件的Fin间距仅有35 nm左右, 且临界电荷降至亚fC, 但FinFET结构的引入导致灵敏区电荷收集和共享机制发生变化, 浅沟道隔离致使电荷扩散通道“狭窄化”, 另一方面灵敏区表面积减小至0.0024 μm², 从而导致14 nm工艺器件SBU和MCU的软错误率均明显下降.

关键词:

FinFET /
中子 /
单粒子翻转 /
软错误

Abstract

Based on the Yangbajing International Cosmic Ray Observatory in Lhasa with an altitude of 4300 m, a long-term real-time experiment is carried out in order to measure the atmospheric radiation induced soft errors in 14 nm FinFET and 28 nm planar CMOS SRAM array. The underlying mechanisms are also revealed. Five boards are used in the test, four of which are equipped with 28-nm process devices, and one board is equipped with 14-nm process devices. After removing the unstable bad bits, the actual effective test capacity is 7.1 Gb. During the test, the on-board FPGA reads the stored contents of all the tested devices in real time, reports the error information (occurrence time, board number, column number, device number, error address, error data) and corrects the error. The duration of the test is 6651 h. A total of 56 single event upset (SEU) events are observed, they being 24 single bit upset (SBU) events and 32 Multiple Cell Upset (MCU) events. Based on previous results of 65-nm SRAM, the study finds that SER continues to decrease with the reduction of process size, but the proportion of MCU in 28-nm process devices (57%) exceeds SBU, which is a process “maximum point” of MCU sensitivity, and the maximum size of MCU is 16 bits. Although the Fin spacing of the 14-nm FinFET device is only about 35 nm, and the critical charge decreases to sub-fC, the introduction of the FinFET structure leads to the change of charge collection and the sensitive volume sharing mechanism , and the shallow trench isolation leads to the narrowing of the charge diffusion channel. On the other hand, the surface area of the sensitive volume decreases to 0.0024 μm², resulting in a significant decrease in the soft error rate of both SBU and MCU in the 14-nm process.

Keywords:

作者及机构信息

1.
工业和信息化部电子第五研究所, 广州　511370

2.
电子元器件可靠性物理及其应用技术国家级重点实验室, 广州　511370

通信作者: 杨少华, young01@163.com ; 林倩, 523618482@qq.com ;

基金项目: 国家自然科学基金(批准号: 12175045, 12075065)和广东省重点领域研发计划(批准号: 2022B0701180002)资助的课题.

Authors and contacts

1.
China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 511370, China

2.
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, Guangzhou 511370, China

Corresponding author: Yang Shao-Hua, young01@163.com ; Lin Qian, 523618482@qq.com ;

Funds: Project supported by the National Natural Science Foundation of China (Grant Nos. 12175045, 12075065) and the Key-Area Research and Development Program of Guangdong Province, China (Grant No. 2022B0701180002).

文章全文 : translate this paragraph

参考文献

[1]	Ziegler J 2004 SER-History, Trends and Challenges (San Jose: Cypress Semiconductor) pp1–50
[2]	JESD89 A 2006 Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices JEDEC standard, October 2006
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施引文献

图 1 羊八井国际宇宙射线观测站

Fig. 1. Yangbajing International Cosmic Ray Observatory.

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图 2 试验现场图及测试结果

Fig. 2. Experimental setup and test results.

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图 3 上位机软件测试界面

Fig. 3. Software test interface on the computer.

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图 4 试验流程图

Fig. 4. Test flow chart.

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图 5 高海拔试验点的大气辐射环境^[3]

Fig. 5. Atmospheric radiation environment of the high-altitude test site^[3].

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图 6 SEU累积计数与TTF的关系图

Fig. 6. Relationship between SEU cumulative count and TTF

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图 7 SEU, SBU和MCU SER与工艺尺寸的关系

Fig. 7. Relationship between SERs of SEU, SBU, MCU and feature size.

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图 8 各种工艺尺寸下的SBU和MCU占比

Fig. 8. Proportion of SBU and MCU under various feature sizes.

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图 9 芬兰奥卢宇宙射线站监测的大气中子通量变化情况(1965年至今)^[24]

Fig. 9. Changes of atmospheric neutron flux monitored by Oulu Cosmic Ray Station in Finland (1965 till now)^[24].

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图 10 试验期间芬兰奥卢宇宙射线站监测的大气中子通量变化情况

Fig. 10. Changes of atmospheric neutron flux monitored by Oulu Cosmic Ray Station in Finland during the test.

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图 11 14 nm FinFET器件的Fin结构图像

Fig. 11. Fin structure of the 14 nm FinFET device.

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图 12 14 nm FinFET器件模型图

Fig. 12. Model of the 14 nm FinFET device.

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图 13 不同入射角下两个器件的单粒子瞬态脉冲图　(a) T1瞬态脉冲; (b) T2瞬态脉冲

Fig. 13. Single event transients of two transistors at different incidence angles: (a) T1 transient pulse; (b) T2 transient pulse.

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表 1 被测器件参数

Table 1. Parameters of devices under test.

编号	SRAM工艺	型号	容量	核心电压/V	测试板编号	测试数量	封装形式	备注
1#	14 nm FinFET	AG35	128 Mbit (8 M×16 bit)	0.8	4#	18只	倒装BGA	总测试容量: 7.1 Gbit (去除坏位)
2#	28 nm HKMG	AH09F	64 Mbit (4 M×16 bit)	1.05	1#、2#	各19只
3#	28 nm SION	AC81	64 Mbit (4 M×16 bit)	1.05	3#、5#	17只、20只

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表 2 测量结果汇总

Table 2. Summary of test results

编号	TTF /h	板号	列号	器件编号	错误地址	错误数据	错误类型
	开始测试
1	—	2#	B	1	0x0C7A70	0x5455	SBU
2	109	3#	B	2	0x06DBBC 0x06DBCC	0x55D5	MCU2
3	190	5#	B	5	0x02B589 0x02B599 0x02B5A9	0x55D5	MCU3
4	460	5#	D	2	0x2CB048	0x555D	SBU
5	528	3#	B	1	0x3C2368	0x5D55	SBU
6	861	1#	B	1	0x0B150F	0x5575	SBU
7	—	2#	A	5	0x12ACC9 0x12ACD9	0x5455	MCU2
8	1128	1#	C	1	0x3C1F74	0x5755	MCU3
					0x3C1F83	0x5755
					0x3C2001	0x5455
9	—	2#	B	4	0x131353 0x131354 0x131363 0x131364	0x7555	MCU4
10	—	2#	A	1	0x040D82 0x040D83 0x040D92 0x040D93	0x5155	MCU4
11	1574	5#	B	3	0x0B5725	0x5551	SBU
12	1583	5#	C	2	0x036145	0x5554	SBU
13	1701	3#	C	4	0x03BBE8 0x03BBE9 0x03BBF8 0x03BBF9	0x5515	MCU4
14	1728	3#	C	4	0x3D4BD8 0x3D4BE8 0x3D4BF7 0x3D4BF8	0x7555	MCU4
15	—	2#	B	3	0x201A55 0x201A65	0x5755	MCU2
16	—	2#	C	1	0x04931E	0x5551	SBU
17	1821	3#	A	2	0x01F573 0x01F574 0x01F583 0x01F584 0x01F593 0x01F594 0x01F5A3 0x01F5E6	0x5557	MCU8
18	1896	5#	D	1	0x377B7B	0x5515	SBU
19	—	2#	C	4	0x1371CB 0x1371EA 0x1371F9 0x1371FA 0x13720A 0x13721A 0x13722A 0x137237 0x137238 0x137247 0x137248 0x137257 0x137258 0x137267 0x137268 0x137277	0xD555	MCU16
20	—	2#	A	5	0x020319 0x020329	0x55D5	MCU2
21	—	2#	B	2	0x1EBD02 0x1EBD12	0x5545	MCU2
22	—	2#	B	2	0x1AA6E8	0x5557	SBU
23	—	2#	D	2	0x35DC4C 0x35DC5C 0x35DC6C	0x555D	MCU3
24	2336	5#	C	2	0x0DB484	0x5554	SBU
25	2537	1#	C	1	0x12C6AE 0x12C6AF 0x12C6BE 0x12C6BF	0x5155	MCU4
26	2631	5#	C	5	0x1157DD 0x1157ED 0x1157EE 0x1157FD 0x1157FE	0x5575	MCU5
27	2659	5#	B	4	0x27B863	0x4555	SBU
28	2898	5#	D	3	0x22C4A8	0x5575	SBU
29	2909	3#	C	1	0x1FC2CE	0x7555	SBU
30	3003	3#	A	2	0x30B1F3 0x30B203 0x30B213	0x5551	MCU3
31	—	2#	C	1	0x2800CA 0x2800D9 0x2800E9	0x5D55	MCU3
32	—	2#	A	4	0x256BB0 0x256BB1 0x256BC0 0x256BC1 0x256BD0 0x256BD1 0x256BE0 0x256BE1	0x4555	MCU8
33	3444	1#	A	5	0x28940C 0x28941C 0x28941D	0x5455	MCU3
34	3577	1#	A	4	0x31B05F	0x5155	SBU
35	3586	1#	B	2	0x1491E7 0x1491E8	0x5575	MCU2
36	3602	3#	C	1	0x250F89 0x250F98	0x5554	MCU2
37	3705	5#	B	3	0x3CAAFA 0x3CAAFB 0x3CAB0A 0x3CAB0B 0x3CAB1A 0x3CAB1B	0x4555	MCU6
38	3775	5#	D	1	0x2CADB4	0x5557	SBU
39	3913	3#	D	1	0x3AC5DD 0x3AC5DE	0x5575	MCU2
40	4191	3#	B	5	0x22DEA3	0x5455	SBU
41	4216	3#	D	2	0x3785ED 0x3785FD	0x4555	MCU2
42	4407	1#	B	2	0x361165	0x5554	SBU
43	4624	4#	A	3	0x64D7B0	0x5D55	SBU
44	4652	1#	A	2	0x001763 0x001754 0x001753	0xD555	MCU3
45	4907	5#	C	5	0x1753E9	0x5575	SBU
46	—	2#	B	5	0x1A220A 0x1A220B 0x1A221A 0x1A221B	0x5155	MCU4
47	5370	5#	A	4	0x0AF8C1 0x0AF8D1 0x0AF8E1 0x0AF8F1	0x555D	MCU4
48	5468	5#	B	5	0x1D4987	0x5755	SBU
	—	3#	C	5	0x0D82B0	0x5545	假SEU
	—	3#	C	5	0x0D82B0	0x5545	假SEU
49	6086	4#	D	4	0x1263CA	0x4555	SBU
50	6094	5#	C	5	0x3ECD72 0x3ECD82	0x5755	MCU2
51	—	2#	D	5	0x27340D 0x27341D 0x27342D 0x27343D	0x5545	MCU4
52	6244	5#	C	3	0x077D9A	0x5545	SBU
53	6244.2	3#	C	3	0x289097	0x5155	SBU
54	—	2#	A	3	0x173626 0x173636	0x5554	MCU2
55	6248.2	5#	B	5	0x177AE1	0x5155	SBU
56	6390.2	5#	C	4	0x04619D 0x0461BC	0x7555	MCU2
	6651.2	试验结束

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表 3 14 nm FinFET, 28 nm和65 nm SRAM的存储单元尺寸和灵敏区参数

Table 3. Memory cell size and SV parameters for the 14 nm FinFET, 28 nm and 65 nm SRAM devices.

器件工艺	65 nm	28 nm	14 nm FinFET
存储区图像(未按比例)
存储单元尺寸	1000 nm×500 nm	520 nm×240 nm	370 nm×180 nm
SV尺寸	200 nm×190 nm	104 nm×90 nm	80 nm×30 nm
临界电荷/fC	1^[25]	0.18^[26]	0.05^[27]

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表 4 14 nm FinFET器件建模的结构参数

Table 4. Structural parameters for modeling 14 nm FinFET device.

区域类别	参数
衬底厚度/nm	100
栅极长度/nm	26
栅氧层厚度/nm	1.35
Fin高/nm	45
Fin宽/nm	14

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表 5 14 nm FinFET器件模型掺杂情况

Table 5. Doping parameters of 14 nm FinFET device model.

掺杂类别	区域	掺杂浓度/(10¹⁶ cm^–3)
均匀掺杂	衬底	1.0 (掺硼)
均匀掺杂	沟道	1.0 (掺硼)
高斯掺杂	漏区	10000.0 (掺磷)
高斯掺杂	源区	10000.0 (掺磷)

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map

[1]	Ziegler J 2004 SER-History, Trends and Challenges (San Jose: Cypress Semiconductor) pp1–50
[2]	JESD89 A 2006 Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices JEDEC standard, October 2006
[3]	张战刚, 雷志锋, 黄云, 恩云飞, 张毅, 童腾, 李晓辉, 师谦, 彭超, 何玉娟, 肖庆中, 李键坷, 路国光 2022 原子能科学技术 56 725 Zhang Z G, Lei Z F, Huang Y, En Y F, Zhang Y, Tong T, Li X H, Shi Q, Peng C, He Y J, Xiao Q Z, Li J K, Lu G G 2022 At. Energy Sci. Technol. 56 725
[4]	Seifert N, Kirsch M 2012 IEEE Trans. Nucl. Sci. 59 2818 Google Scholar
[5]	Autran J L, Munteanu D, Serre S, Sauze S 2012 IEEE International Reliability Physics Symposium (IRPS) Anaheim, CA, April 15–19, 2012 p5B.1.1
[6]	Autran J L, Roche P, Borel J, Sudre C, Castellani-Coulié K, Munteanu D, Parrassin T, Gasiot G, Schoellkopf J P 2007 IEEE Trans. Nucl. Sci. 54 1002 Google Scholar
[7]	Autran J L, Roche P, Sauze S, Gasiot G, Munteanu D, Loaiza P, Zampaolo M, Borel J 2009 IEEE Trans. Nucl. Sci. 56 2258 Google Scholar
[8]	Autran J L, Munteanu D, Roche P, Gasiot G, Martinie S, Uznanski S, Sauze S, Semikh S, Yakushev E, Rozov S, Loaiza P, Warot G, Zampaolo M 2010 Microelectron. Reliab. 50 1822 Google Scholar
[9]	Xilinx, Device reliability report (UG116), https://www.xilinx.com/ [2023-2-1]
[10]	Lesea A, Drimer S, Fabula J J, Carmichael C, Alfke P 2005 IEEE Trans. Device Mater. Reliab. 5 317 Google Scholar
[11]	White paper: Xilinx FPGA families, “Continuing experiments of atmospheric neutron effects on deep submicron integrated circuits” WP286 (v2.0), Mar. 22, 2016
[12]	王勋, 张凤祁, 陈伟, 郭晓强, 丁李利, 罗尹虹 2019 68 052901 Google Scholar Wang X, Zhang F Q, Chen W, Guo X Q, Ding L L, Luo Y H 2019 Acta Phys. Sin. 68 052901 Google Scholar
[13]	Chen W, Guo X, Wang C, Zhang F, Qi C, Wang X, Jin X, Wei Y, Yang S, Song Z 2019 IEEE Trans. Nucl. Sci. 66 856 Google Scholar
[14]	Hubert G, Velazco R, Federico C, Cheminet A, Silva-Cardenas C, Caldas L V E, Pancher F, Lacoste V, Palumbo F, Mansour W, Artola L, Pineda F, Duzellier S 2013 IEEE Trans. Nucl. Sci. 60 2418 Google Scholar
[15]	Alexandrescu D, Lhomme-Perrot A, Schaefer E, Beltrando C 2009 15th IEEE International On-Line Testing Symposium Sesimbra, Lisbon, Portugal, June 24–26, 2009 p179
[16]	Torok Z, Platt S P, Cai X X 2007 9th European Conference on Radiation and Its Effects on Components and Systems Deauville, France, September 10–14, 2007 p1
[17]	Tosaka Y, Takasu R, Uemura T, Ehara H, Matsuyama H, Satoh S, Kawai A, Hayashi M 2008 IEEE International Reliability Physics Symposium Phoenix, AZ, USA, April 27–May 1, 2008 p727
[18]	Kameyama H, Yahagi Y, Ibe E 2007 IEEE International Reliability Physics Symposium Phoenix, AZ, USA, April 15–19, 2007 p678
[19]	Ibe E, Yahagi Y, Kataoka F, Saito Y, Eto A, Sato M 2002 ICITA Bathurst, Australia, November 25–28, 2002 No. 273-21
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基于青藏高原的14 nm FinFET和28 nm平面CMOS工艺SRAM单粒子效应实时测量试验