硅纳米结构晶体管中与杂质量子点相关的量子输运

吴歆宇; 韩伟华; 杨富华

doi:10.7498/aps.68.20190095

摘要

在小于10 nm的沟道空间中, 杂质数目和杂质波动范围变得十分有限, 这对器件性能有很大的影响. 局域纳米空间中的电离杂质还能够展现出量子点特性, 为电荷输运提供两个分立的杂质能级. 利用杂质原子作为量子输运构件的硅纳米结构晶体管有望成为未来量子计算电路的基本组成器件. 本文结合安德森定域化理论和Hubbard带模型对单个、分立和耦合杂质原子系统中的量子输运特性进行了综述, 系统介绍了提升杂质原子晶体管工作温度的方法.

关键词:

Abstract

As the characteristic size of the transistor approaches to its physical limit, the effect of impurities on device performance becomes more and more significant. The number of impurities and the range of impurity fluctuation become very limited in channel space less than 10 nm, and ionized impurities in local nano-space can even exhibit quantum dot characteristics, providing two discrete levels for charge transport. The behaviour of carrier tunnelling through quantum dots induced by ionized impurities can reveal the abundant quantum information, such as impurity ionization energy, coulomb interaction energy, electron activation energy, orbital level filling, and spin of local electrons. Quantum transport properties are also different in different doping concentrations because whether the quantum states overlap depends on the impurity atom spacing. The silicon nanostructure transistors using impurity atoms as building blocks of quantum transport are also called dopant atom transistors, which are not only compatible with complementary metal oxide semiconductor (CMOS) technology, but also expected to be the basic components of quantum computing circuits in the future. So far, their operating temperature is relatively low due to the shallow ground state energy level of impurity atoms. It is of great significance to study the quantum transport properties in dopant atom transistors and to observe quantum effects among them at room temperature. In this article, the quantum transport properties in single, discrete and coupled impurity atomic systems are described in detail by combining Anderson localization theory and Hubbard band model. Quantum transport in a discrete impurity atomic system is not only controlled by gate voltage, but also dependent on temperature. The current transport spectrum in the coupled impurity atomic system reveals more complex quantum dot characteristics. Single atom transistor can regulate quantum transport only by one impurity atom, which represents the ultimate scale limit of solid state devices. In addition, the methods of improving the operating temperature of dopant atom transistors are also systematically introduced, thereby laying a foundation for their practical applications.

Keywords:

作者及机构信息

1.
中国科学院半导体研究所, 半导体集成技术工程研究中心, 北京市半导体微纳集成工程技术研究中心, 北京　100083

2.
中国科学院大学, 材料与光电研究中心, 北京　100049

通信作者: 韩伟华, weihua@semi.ac.cn

基金项目: 国家重点研发计划(批准号: 2016YFA0200503)资助的课题.

Authors and contacts

1.
Engineering Research Center of Semiconductor Integrated Technology, Beijing Engineering Research Center of Semiconductor Micro-Nano Integrated Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

2.
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

Corresponding author: Han Wei-Hua, weihua@semi.ac.cn

Funds: Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200503).

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施引文献

图 1 电离杂质形成的势阱结构^[19]

Fig. 1. Confinement potential induced by ionizing impurity^[19].

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图 2 理想单杂质晶体管的基本结构和工作原理图　(a)单杂质晶体管结构示意图; (b)施主原子调制源端到漏端的单电子隧穿; (c)低温下单杂质晶体管的转移特性曲线^[25]

Fig. 2. Structure and schematic diagram of the ideal single-dopant transistor: (a) Schematic illustration of single-dopant transistor; (b) donor mediates single-electron tunneling from source to drain; (c) transfer characteristics for single-dopant transistor in the low temperature^[25].

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图 3 (a)单原子晶体管器件结构 STM 图像; (b)局部放大图^[28]

Fig. 3. (a) Perspective STM image of single-atom transistor; (b) close-up of the inner device area^[28].

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图 4 (a)短沟道器件示意图; (b)短沟道器件电势分布图; (c)短沟道器件I_sd -V_g特性曲线(V_sd = 5 mV); (d)长沟道器件示意图; (e)长沟道器件电势分布图; (f)长沟道器件I_sd -V_g特性曲线(V_sd = 5 mV)^[29]

Fig. 4. (a) Schematic channel structure; (b) example of simulated potential profile; (c) example of dc I_sd -V_g characteristics (V_sd = 5 mV) for a short-channel FET; (d) schematic channel structure; (e) example of simulated potential profile; (f) example of dc I_sd -V_g chara-cteristics (V_sd = 5 mV) for a long-channel FET^[29].

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图 5 (a)不同沟道长度下分裂峰个数的实验统计; (b)不同沟道长度下量子点个数的模拟统计; (c) 50 nm × 50 nm纳米结构中一个量子点中的平均杂质数目^[29]

Fig. 5. (a) Statistical results of the number of subpeaks; (b) statistical results of the number of dopant-induced QDs; (c) average number of dopants embedded in one QD for 50 nm × 50 nm nanostructures^[29].

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图 6 (a)低温下随栅压变化的电势分布图; (b)分立的磷施主原子在不同栅压下逐个电中性化^[30]

Fig. 6. (a) Sequence of electronic potential landscapes as a function of applied V_BG; (b) a simple illustration of one-by-one neutralization of individual P-donors at different V_BG^[30].

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图 7 (a) SOI-FET低温下的I_D-V_G特性曲线; (b)沟道中可能的杂质原子分布以及沟道电势分布示意图^[31]

Fig. 7. (a) Low-temperature source-drain current (I_D) vs. gate voltage (V_G) characteristics; (b) one possible P-donors’ distribution and schematic channel potential profiles^[31].

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图 8 无序系统中的带尾定域态^[32]

Fig. 8. Tailed localized states in disordered systems^[32].

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图 9 弱杂质补偿和强杂质补偿情况下的能带和定域态空间分布示意图　(a)弱杂质补偿; (b)强杂质补偿^[34]

Fig. 9. Schematic representation of the energy and space distribution of the localized states in the case of weak (a) and strong (b) compensation^[34].

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图 10 电子的跃迁方式　(a)可变程跃迁; (b)最近邻跃迁^[38]

Fig. 10. Hopping modes of the electron: (a) Variable range hopping; (b) nearest neighbor hopping^[38].

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图 11 (a)开尔文探针力显微镜测量SOI-FETs的结构示意图; (b), (c)不同掺杂浓度下, 施主原子形成的电势分布图^[39]

Fig. 11. (a) Schematic of KPFM measurement setup; (b), (c) potential distribution of donor atoms at different doping concentrations^[39]

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图 12 (a) SOI-FET低温下的I_D-V_G特性曲线; (b)选择性掺杂沟道中可能的杂质原子分布以及沟道电势分布示意图^[31]

Fig. 12. (a) Low-temperature source-drain current (I_D) vs gate voltage (V_G) characteristics; (b) a possible P-donors’ distribution and schematic channel potential profiles in the selective doping channel^[31].

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图 13 Hubbard能带模型^[43]

Fig. 13. Hubbard band model^[43].

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图 14 不同杂质数目下的量子输运特征, 从单施主态到杂质带的安德森-莫特转变^[44]

Fig. 14. Anderson-Mott transition probed by means of quantum transport^[44].

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图 15 (a)沿沟道分布的20个磷施主原子中电势分布的理想示意图; (b)V_ds = 2.505 mV时, 在4.4 K下测量的器件电导-栅压曲线. 插图: V_ds = 2.505 mV时, 室温下提取的阈值电压^[45]

Fig. 15. (a) An idealized representation of the potential distributions in the 20 phosphorous donors distributed along the channel of the sample; (b) conductance σ of the device probed at 4.4 K measured at V_ds = 2.505 mV. Inlet: extraction of the threshold voltage at room temperature, at V_ds = 2.505 mV^[45].

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图 16 (a)4.2—274 K温度区间下的电导-栅压曲线; (b)高温下上Hubbard带的热激活输运; (c)低温下下Hubbard带的热激活输运; (d)低温下上Hubbard带的热激活输运^[45]

Fig. 16. (a) The conductance as a function of the gate voltage V_g from 4.2 to 274 K; (b) the thermal activation of the upper Hubbard band at high temperature; (c) the thermal activation of the lower Hubbard band at low temperature; (d) the thermal activation of the upper Hubbard band at low temperature^[45].

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图 17 (a)单电子晶体管结构示意图; (b)化学湿法腐蚀后硅纳米线扫描电子显微镜(SEM)图; (c)形成围栅GAA结构后硅纳米线透射电子显微镜(TEM)图; (d)制备的单电子晶体管在150−300 K下的I_D-V_G特性曲线^[52]

Fig. 17. (a) Schematic configuration of the fabricated Si SET; (b) scanning electron microscopy image of the Si nanowire after chemical wet-etching; (c) transmission electron microscopy image of the Si nanowire after fabricating the GAA structure; (d) I_D−V_G characteristic curves of the fabricated SET at T = 150−300 K^[52].

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图 18 (a)杂质原子晶体管结构示意图; (b)杂质在器件沟道中提供确定的两个能级^[19]

Fig. 18. (a) Schematic of dopant atom transistor; (b) two determined levels provided by impurity in device^[19].

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图 19 磷原子的基态能级随硅纳米线直径的减小而加深^[53]

Fig. 19. Ground state of phosphorous donor becomes deeper with decreasing radius of Si nanowire^[53].

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图 20 (a)没有和(b)有介电限制时杂质原子的电离能随纳米线半径的变化曲线图^[55]

Fig. 20. Ionization energy E_I vs. the wire radius R for donor impurities: (a) Without dielectric confinement; (b) with dielectric confinement^[55].

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图 21 (a) SOI晶体管结构示意图; (b)器件沟道TEM图; (c)原纳米线结构; (d) stub纳米线结构^[57]

Fig. 21. (a) Schematic of SOI transistor; (b) TEM image taken across the device channel; (c) SEM images of non-stub channel and (d) stub channel^[57].

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图 22 基态电子的束缚能随耦合原子数目的增加而增大^[53]

Fig. 22. Binding energy of clustered donors is shown for different N^[53].

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图 23 (a)选择性掺杂硅纳米沟道; (b)选择性掺杂区域模拟的最深势阱分布^[58]

Fig. 23. (a) The selectively-doped Si nanoscale channel; (b) atomistic representation of the potential landscape simulated for a selectively-doped area with deepest potential well^[58].

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图 24 (a)沟道选择性掺杂和(b)沟道未掺杂SOI-FET在不同温度下的I_D-V_G特性曲线^[58]

Fig. 24. (a) and (b) IDS-VG characteristics as a function of temperature for a selectively-doped-channel SOI-FET (up to 300 K) and for a non-doped-channel SOI-FET (up to 160 K)^[58].

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图 25 (a)不同温度下, 沟道选择性掺杂SOI-FET器件I_DS-V_G特性曲线; (b)有效势垒高度随栅压V_G的变化; (c)不同电流峰对应的Arrhenius曲线; (d)激活传导的库仑阻塞机制(下图), 量子点俘获电子的库仑阻塞情形(上图); (e)沟道未掺杂SOI-FET器件仅仅表现出热激活传导性质^[58]

Fig. 25. (a) I_DS-V_G characteristics as a function of temperature for the selectively-doped channel SOI-FET; (b) effective barrier height (E_Beff) estimated from Arrhenius plots as a function of V_G; (c) arrhenius plots for V_G corresponding to different peaks; (d) schematic illustrations of the mechanism of Coulomb blockade of activated conduction for the single-electron tunneling current peak (lower panel) and for the Coulomb blockade condition with an electron trapped in the QD (upper panel); (e) E_Beff extracted for a non-doped-channel SOI-FET, exhibiting only behavior typical of thermally-activated conduction^[58].

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图 26 (a)点接触式量子点晶体管结构示意图; (b)点接触区域的能带示意图^[62]

Fig. 26. (a) Schematic of the point contact QD transistor; (b) schematic representation of the energy diagram across the point-contact region^[62].

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map

[1]	Chan V, Rengarajan R, Rovedo N, Wei J 2003 Proceedings of IEEE International Electron Devices Meeting Washington USA, December 8−10, 2003 p381
[2]	Mistry K, Allen C, Auth C 2007 Proceedings of IEEE International Electron Devices Meeting Washington USA, December 10−12, 2007 p247
[3]	Auth C, Allen C, Blattner A 2012 Proceedings of Symposium on VLSI Technology Honolulu USA, June 12−14, 2012 p131
[4]	Colinge J P, Lee C W, Afzalian A, Akhavan N D, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M 2010 Nature Nanotech. 5 225 Google Scholar
[5]	Lee C W, Afzalian A, Akhavan N D, Yan R, Ferain I, Colinge J P 2009 Appl. Phys. Lett. 94 053511 Google Scholar
[6]	黎明, 黄如 2018 中国科学: 信息科学 48 963 Li M, Huang R 2018 Sci. Sin. Inform. 48 963
[7]	Asenov A, Watling J R, Brown A R, Ferry D K 2002 J. Comput. Electron. 1 503 Google Scholar
[8]	Taur Y 2002 IBM J. Res. Dev. 46 213 Google Scholar
[9]	李艳萍, 徐静平, 陈卫兵, 许胜国, 季峰 2006 55 3670 Google Scholar Li Y P, Xu J P, Chen W B, Xu S G, Ji F 2006 Acta Phys. Sin. 55 3670 Google Scholar
[10]	曹磊, 刘红侠 2012 61 247303 Google Scholar Cao L, Liu H X 2012 Acta Phys. Sin. 61 247303 Google Scholar
[11]	Je M, Han S, Kim I, Shin H 2000 Solid-State Electron. 44 2207 Google Scholar
[12]	Warren A C, Antoniadis D, Smith H I 1986 Phys. Rev. Lett. 56 1858 Google Scholar
[13]	Rustagi S C, Singh N 2007 IEEE Electr. Device L. 28 909 Google Scholar
[14]	Colinge J P, Xiong W 2006 IEEE Electr. Device L. 27 775 Google Scholar
[15]	Park J T, Kim J Y 2010 Appl. Phys. Lett. 97 172101 Google Scholar
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