基于双电源电压和双阈值电压的全局互连性能优化

董刚; 刘嘉; 薛萌; 杨银堂

doi:10.7498/aps.60.046602

摘要

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计.

关键词:

Abstract

Based on dual supply and dual threshold voltages technique, a novel methodology optimizing global interconnect performance in presented in this paper. The new figure of merit (FOM) is first defined as a function of bandwidth, delay and power consumption of global interconnect. Then, the optimal dual voltages can be obtained to save interconnect power by maximizing FOM function within a given delay penalty. Simulations show that in 65 nm technology, for the allowed delay penalties of 5%, 10% and 20%, the proposed methodology saves 27.8%, 40.3% and 56.9% power compared with the case with single supply and single threshold voltages, respectively. It can also be found that more power savings are achieved with the technology improving. The proposed methodology can be used to design and optimize global interconnects.

Keywords:

作者及机构信息

1.
西安电子科技大学微电子所宽禁带半导体材料与器件教育部重点实验室,西安 710071

基金项目: 国家自然科学基金(批准号:60606006),国家杰出青年基金(批准号:60725415)和西安电子科技大学基本科研业务费资助的课题.

Authors and contacts

1.
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,Microelectronics Institute, Xidian University, Xi'an 710071

参考文献

[1]	Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 (in Chinese) [王俊平、郝跃 2009 58 4267]
[2]	Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 (in Chinese) [李鑫、Janet M Wang、唐卫清 2009 58 3603]
[3]	Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 58 2631]
[4]	Li X C, Mao J F, Huang H F, Liu Y 2005 IEEE Transactions on Electron Devices 52 2272
[5]	Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[6]	Banerjee K, Mehrotra A 2002 IEEE Transactions on Electron Devices 49 2001
[7]	Naeemi A, Venkatesan R, Meindl J D 2004 IEEE Transactions on Electron Devices 51 980
[8]	Mui M L, Banerjee K, Mehrotra A 2004 IEEE Transactions on Electron Devices 51 195
[9]	Zhu Z M, Hao B T, Li R, Yang Y T 2010 Acta Phys. Sin. 59 1997 (in Chinese) [朱樟明、郝报田、李儒、杨银堂 2010 59 1997]
[10]	Ku J C, Ismail Y 2007 IEEE Transactions on VLSI Systems 15 963
[11]	Zhu Z M, Zhong B, Hao B T, Yang Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明、钟波、郝报田、杨银堂 2009 58 7124]
[12]	Tam K H, Hu Y, He L 2008 IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27 1498
[13]	Chang Y C, Tam K H, He L 2005 Proc. ISLPED, San Diego, USA, August 8—10, p137
[14]	Diril A U, Dhillon Y S, Chatterjee A, Singh A D 2005 IEEE Transactions on VLSI Systems 13 1103
[15]	Bakoglu H B, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990
[16]	Chen G, Friedman E Proc.International ASJC/SOC Conference, Santa Clara, USA, September 12—15, p335
[17]	Wong S C, Lee G Y, Ma D J 2000 IEEE Transactions on Semiconductor Manufacturing 13 108
[18]	Kim K K, Kim Y B 2009 IEEE Transactions on VLSI Systems 17 517
[19]	Amelifard B, Fallah F, Pedram M 2008 IEEE Transactions on VLSI Systems 16 851

施引文献

[1]	Wang J P, Hao Y 2009 Acta Phys. Sin. 58 4267 (in Chinese) [王俊平、郝跃 2009 58 4267]
[2]	Li X, Wang J M, Tang W Q 2009 Acta Phys. Sin. 58 3603 (in Chinese) [李鑫、Janet M Wang、唐卫清 2009 58 3603]
[3]	Zhu Z M, Qian L B, Yang Y T 2009 Acta Phys. Sin. 58 2631 (in Chinese) [朱樟明、钱利波、杨银堂 2009 58 2631]
[4]	Li X C, Mao J F, Huang H F, Liu Y 2005 IEEE Transactions on Electron Devices 52 2272
[5]	Zhu Z M, Qian L B, Yang Y T 2009 Chin. Phys. B 18 1188
[6]	Banerjee K, Mehrotra A 2002 IEEE Transactions on Electron Devices 49 2001
[7]	Naeemi A, Venkatesan R, Meindl J D 2004 IEEE Transactions on Electron Devices 51 980
[8]	Mui M L, Banerjee K, Mehrotra A 2004 IEEE Transactions on Electron Devices 51 195
[9]	Zhu Z M, Hao B T, Li R, Yang Y T 2010 Acta Phys. Sin. 59 1997 (in Chinese) [朱樟明、郝报田、李儒、杨银堂 2010 59 1997]
[10]	Ku J C, Ismail Y 2007 IEEE Transactions on VLSI Systems 15 963
[11]	Zhu Z M, Zhong B, Hao B T, Yang Y T 2009 Acta Phys. Sin. 58 7124 (in Chinese) [朱樟明、钟波、郝报田、杨银堂 2009 58 7124]
[12]	Tam K H, Hu Y, He L 2008 IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27 1498
[13]	Chang Y C, Tam K H, He L 2005 Proc. ISLPED, San Diego, USA, August 8—10, p137
[14]	Diril A U, Dhillon Y S, Chatterjee A, Singh A D 2005 IEEE Transactions on VLSI Systems 13 1103
[15]	Bakoglu H B, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990
[16]	Chen G, Friedman E Proc.International ASJC/SOC Conference, Santa Clara, USA, September 12—15, p335
[17]	Wong S C, Lee G Y, Ma D J 2000 IEEE Transactions on Semiconductor Manufacturing 13 108
[18]	Kim K K, Kim Y B 2009 IEEE Transactions on VLSI Systems 17 517
[19]	Amelifard B, Fallah F, Pedram M 2008 IEEE Transactions on VLSI Systems 16 851

[1]	黄玉凤, 吴卫华, 徐胜卿, 朱小芹, 宋三年, 宋志棠. Sn₁₅Sb₈₅相变薄膜的厚度效应. , 2021, 70(22): 226102. doi: 10.7498/aps.70.20210973
[2]	张岩, 董刚, 杨银堂, 王宁, 王凤娟, 刘晓贤. 考虑自热效应的互连线功耗优化模型. , 2013, 62(1): 016601. doi: 10.7498/aps.62.016601
[3]	周春宇, 张鹤鸣, 胡辉勇, 庄奕琪, 舒斌, 王斌, 王冠宇. 应变Si NMOSFET阈值电压集约物理模型. , 2013, 62(7): 077103. doi: 10.7498/aps.62.077103
[4]	李立, 刘红侠, 杨兆年. 量子阱Si/SiGe/Sip型场效应管阈值电压和沟道空穴面密度模型. , 2012, 61(16): 166101. doi: 10.7498/aps.61.166101
[5]	李妤晨, 张鹤鸣, 张玉明, 胡辉勇, 徐小波, 秦珊珊, 王冠宇. 新型高速半导体器件IMOS阈值电压解析模型. , 2012, 61(4): 047303. doi: 10.7498/aps.61.047303
[6]	强蕾, 姚若河. 非晶硅薄膜晶体管沟道中阈值电压及温度的分布. , 2012, 61(8): 087303. doi: 10.7498/aps.61.087303
[7]	钱利波, 朱樟明, 杨银堂. 一种考虑硅通孔电阻-电容效应的三维互连线模型. , 2012, 61(6): 068001. doi: 10.7498/aps.61.068001
[8]	王冠宇, 张鹤鸣, 王晓艳, 吴铁峰, 王斌. 亚100 nm应变Si/SiGe nMOSFET阈值电压二维解析模型. , 2011, 60(7): 077106. doi: 10.7498/aps.60.077106
[9]	董刚, 薛萌, 李建伟, 杨银堂. 考虑工艺波动的RC互连树统计功耗. , 2011, 60(3): 036601. doi: 10.7498/aps.60.036601
[10]	屈江涛, 张鹤鸣, 王冠宇, 王晓艳, 胡辉勇. 多晶SiGe栅量子阱pMOSFET阈值电压模型. , 2011, 60(5): 058502. doi: 10.7498/aps.60.058502
[11]	刘红侠, 尹湘坤, 刘冰洁, 郝跃. 应变绝缘层上硅锗p型金属氧化物场效应晶体管的阈值电压解析模型. , 2010, 59(12): 8877-8882. doi: 10.7498/aps.59.8877
[12]	朱樟明, 钟波, 杨银堂. 基于RLCπ型等效模型的互连网络精确焦耳热功耗计算. , 2010, 59(7): 4895-4900. doi: 10.7498/aps.59.4895
[13]	李劲, 刘红侠, 李斌, 曹磊, 袁博. 高k栅介质应变Si SOI MOSFET的阈值电压解析模型. , 2010, 59(11): 8131-8136. doi: 10.7498/aps.59.8131
[14]	朱樟明, 钟波, 郝报田, 杨银堂. 一种考虑温度的分布式互连线功耗模型. , 2009, 58(10): 7124-7129. doi: 10.7498/aps.58.7124
[15]	张志锋, 张鹤鸣, 胡辉勇, 宣荣喜, 宋建军. 应变Si沟道nMOSFET阈值电压模型. , 2009, 58(7): 4948-4952. doi: 10.7498/aps.58.4948
[16]	汤晓燕, 张义门, 张玉明. SiC肖特基源漏MOSFET的阈值电压. , 2009, 58(1): 494-497. doi: 10.7498/aps.58.494
[17]	张鹤鸣, 崔晓英, 胡辉勇, 戴显英, 宣荣喜. 应变SiGe SOI量子阱沟道PMOSFET阈值电压模型研究. , 2007, 56(6): 3504-3508. doi: 10.7498/aps.56.3504
[18]	李艳萍, 徐静平, 陈卫兵, 许胜国, 季峰. 考虑量子效应的短沟道MOSFET二维阈值电压模型. , 2006, 55(7): 3670-3676. doi: 10.7498/aps.55.3670
[19]	代月花, 陈军宁, 柯导明, 孙家讹. 考虑量子化效应的MOSFET阈值电压解析模型. , 2005, 54(2): 897-901. doi: 10.7498/aps.54.897
[20]	汤晓燕, 张义门, 张玉明. 界面态电荷对6H碳化硅N沟MOSFET阈值电压和跨导的影响. , 2002, 51(4): 771-775. doi: 10.7498/aps.51.771

计量

文章访问数: 8123
PDF下载量: 651
被引次数: 0

姓名
邮箱
手机号码
标题
留言内容
验证码

搜索

留言板