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人工智能的快速发展需要人工智能专用硬件的快速发展, 受人脑存算一体、并行处理启发而构建的包含突触与神经元的神经形态计算架构, 可以有效地降低人工智能中计算工作的能耗. 记忆元件在神经形态计算的硬件实现中展现出巨大的应用价值; 相比传统器件, 用忆阻器构建突触、神经元能极大地降低计算能耗, 然而在基于忆阻器构建的神经网络中, 更新、读取等操作存在由忆阻电压电流造成的系统性能量损失. 忆容器作为忆阻器衍生器件, 被认为是实现低耗能神经网络的潜在器件, 引起国内外研究者关注. 本文综述了实物/仿真忆容器件及其在神经形态计算中的最新进展, 主要包括目: 前实物/仿真忆容器原理与特性, 代表性的忆容突触、神经元及神经形态计算架构, 并通过总结近年来忆容器研究所取得的成果, 对当前该领域面临的挑战及未来忆容神经网络发展的重点进行总结与展望.The rapid development of artificial intelligence (AI) requires one to speed up the development of the domain-specific hardware specifically designed for AI applications. The neuromorphic computing architecture consisting of synapses and neurons, which is inspired by the integrated storage and parallel processing of human brain, can effectively reduce the energy consumption of artificial intelligence in computing work. Memory components have shown great application value in the hardware implementation of neuromorphic computing. Compared with traditional devices, the memristors used to construct synapses and neurons can greatly reduce computing energy consumption. However, in neural networks based on memristors, updating and reading operations have system energy loss caused by voltage and current of memristors. As a derivative of memristor, memcapacitor is considered as a potential device to realize a low energy consumption neural network, which has attracted wide attention from academia and industry. Here, we review the latest advances in physical/simulated memcapacitors and their applications in neuromorphic computation, including the current principle and characteristics of physical/simulated memcapacitor, representative synapses, neurons and neuromorphic computing architecture based on memcapacitors. We also provide a forward-looking perspective on the opportunities and challenges of neuromorphic computation based on memcapacitors.
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Keywords:
- memcapacitor /
- memcapacitive mechanism /
- synapse /
- neural networks
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图 4 Au/Ti/HfOx/InP结构忆容器[37] (a) 器件结构及总I-V曲线; (b) 零偏压下器件能带结构; (c) 器件
$ {\rm{R}}{\rm{C}} $ 等效电路及C-V曲线; (d) 器件R-V曲线Fig. 4. Structure of Au/Ti/HfOx/InP memcapacitor[37]: (a) device structure and total I-V curves; (b) schematics for the band diagram of the metal HfO2-semiconductordiode at zero bias; (c) equivalent circuit of device and its C-V curves; (d) R-V curves.
图 5 室温下Pt/Pr0.7Ca0.3MnO3(PCMO)/YBCO/LAO结构忆容器性质[28] (a) 非易失电容随脉冲电压数的变化; (b) 非易失电阻随脉冲电压数的变化; (c) 非易失电容随测试电压频率的变化
Fig. 5. Nonvolatile capacitance and resistance changes for Au/PCMO/YBCO/LAO structure sample at room temperature[28]: (a) Nonvolatile capacitance changes with applied pulse numbers; (b) nonvolatile resistance changes with applied pulse numbers; (c) nonvolatile capacitance changes with frequency.
图 6 (a) Ag(TE)/MoOx/MoS2/Ag(BE)忆容器件结构[24]; (b)钼氧化态MoOx/MoS2样品在200 ℃持续3 h退火后的XPS剖面; 填充区域代表一个Mo6 +丰富的区域[24]; (c)电阻、电容开关性质[24]
Fig. 6. [24](a) Ag(TE)/MoOx/MoS2/Ag(BE) structure memcapacitor[24]; (b) Molybdenum oxidation-state XPS profile of the MoOx/MoS2 sample annealed at 200 ℃ for 3 h; the filled area represents a Mo6+ -rich region[24]; (c) capacitance and resistance switch characteristics[24].
图 7 (a)Al/Ti/RbAg4I5 /MEH-PPV/SiO2 /p-Si/Al忆容器结构及其特性曲线[26]; (b) ITO/MASnBr3/Au结构图[61]; (c) ITO/MASnBr3/Au原理图[61]; (d) ITO/MASnBr3/Au结构的忆容特性(1 MHz下的C-V与Q-V特性)[61]; (e) 硅底电极保持接地的有机薄膜记忆电容的器件结构和正负偏压下的电荷积累方案[60]
Fig. 7. (a) A memory capacitor with an Al/Ti/RbAg4I5 /MEH-PPV/SiO2 /p-Si/Al structure (inset) and its characteristic curve[26]; (b) schematic diagram of the ITO/MASnBr3/Au structure[61]; (c) mechanism of the ITO/MASnBr3/Au structure[61]; (d) memcapacitive characteristics of the ITO/MASnBr3/Au device(C-V hysteresis and Q-V loops detected at 1 MHz); (e) device structure and charge accumulation scheme under negative (top) and positive (bottom) biases of an organic thin film memcapacitor, where the Si bottom electrode is kept grounded[60].
图 8 基于记忆电容的人工突触短期塑性模拟[27] (a) 生物突触和Al/共聚物/ITO人工突触装置信号传输示意图, 共聚物薄膜的AFM图像; (b) C-V曲线; (c) 器件的PPF行为, A1和A2分别代表第一个和第二个突触前突起的PSC, 红色和蓝色曲线分别代表正、负电压下的兴奋性PSC和抑制性PSC; (d) PPF指数被绘制成时间间隔的函数
Fig. 8. Short-term plasticity emulated in artificial synapse based on memory capacitance[27]: (a) Schematic illustrations of the signal transmission in biological synapse and the Al/copolymer/ITO artificial synaptic device. AFM image of copolymer film; (b) the C-V curves; (c) PPF behaviors of the device. A1 and A2 represent the PSC of the first and second presynaptic spike, respectively. The red and blue curves represent the excitatory and inhibitory PSC under negative and positive voltage, respectively. The inset shows schematic of pulse application; (d)PPF index plotted as a function of the time interval.
图 9 带[Ru(L)2](PF6)2层器件的测试结构及电学特性[25] (a) 3种结构的示意图; (b)—(d) A(b), B (c)和C (d)结构电流密度对电压J(V)的特性; (e)—(f) 顶部面板显示了结构A(e)和B(f)的相对介电常数与电压的特性, 并覆盖了相应结构的J(V)曲线; 底部的面板显示了结构A(e)和B(f)对应的电荷和电压曲线
Fig. 9. Test structures and electrical characterizations of devices with [Ru(L)2](PF6)[25]: (a) Schematic illustration of the three structures; (b)–(d) the current density versus voltage J(V) characteristics of structures A(b), B(c) and C(d); (e)–(f) the top panels show the relative permittivity versus voltage characteristics of structures A(e) and B(f), overlaid with the J(V) curves of the corresponding structures. The bottom panels show the corresponding charge versus voltage profiles for structures A(e) and B(f).
图 12 生物忆容器仿生膜组装与电行为[30] (a) 一种模拟生物膜结构的电容平面脂质双分子层, 在脂质包被的微滴之间接触并排除多余油脂后自发形成; (b) 由静膜电压v(t)引起的几何变化示意图
Fig. 12. Biomimetic membrane assembly and electromechanical behaviours[30]: (a) A capacitive planar lipid bilayer that mimics the structure of a biological membrane forms spontaneously upon contact between lipid-coated droplets and exclusion of excess oil; (b) a schematic describing the geometrical changes caused by a net membrane voltage, v(t).
图 13 伪忆容[20] (a) 伪忆容的扫描电子显微图的平面视图和透射电子显微图的截面图; (b)集成伪忆容的电荷-电压关系
Fig. 13. Dynamic pseudo-memcapacitor(DPM)[20]: (a) a scanning electron micrograph of the plan view of the integrated DPM, and a transmission electron micrograph of the cross-section; (b) charge-voltage relationship of the integrated DPM.
图 18 伪忆容突触[20] (a) 生物神经元接受高频突触后输入后产生动作电位的示意图; (b) 伪忆容的集成和触发过程; (c) 电子神经元晶体管的原理图; (d) 电子神经元-晶体管集成-点火过程的动力学
Fig. 18. Pseudo-memcapacitor synapse[20]: (a) Schematic representation of a biological neuron generating an action potential after receiving high-frequency post-synaptic inputs; (b) the integrate-and-fire process of a pseudo-memcapacitor synapse; (c) schematic of the synapse-transistor; (d) dynamics of the synapse-transistor integrate-and-fire process.
图 20 MC-ACU[21] (a) 全结构电路图; (b) sigmoid神经元电路; (c) 在HSPICE中的仿真曲线(蓝)与理论数学曲线(红)对比; (d) 线性神经元电路; (e)在HSPICE中的仿真曲线(蓝)与理论数学曲线(红)对比
Fig. 20. MC-ACU[21]: (a) Overall architecture; (b) sigmoid neuron circuit; (c) simulation results in HSPICE (blue) compared with the mathematical sigmoid(red); (d) linear neuron circuit; (e) simulation results in HSPICE (blue) compared with the mathematical linear (red).
图 21 基于电容式网络的联想学习机制[20]. 两个突触前信号分别模拟食物的视觉和铃声. 突触后神经元模拟狗的唾液分泌. 与“食物”突触前神经元连接的突触的初始权重较大, 而与“钟”突触前神经元连接的突触的初始权重较小
Fig. 21. Capacitive network for associative learning based on the Hebbian-like mechanism[20]. Two pre-synaptic signals model the sight of food and the sound of a bell, respectively. The post-synaptic neuron models the salivation of a dog. The initial weight of the synapse interfacing with the “food” pre-synaptic neuron was large, while that of the synapse connected to the “bell” pre-synaptic neuron was small
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[7] Dev D, Krishnaprasad A, Shawkat M S, He Z, Das S, Fan D, Chung H S, Jung Y, Roy T 2020 IEEE Electron Device Lett. 41 936Google Scholar
[8] He C, Tang J, Shang D S, Tang J, Xi Y, Wang S, Li N, Zhang Q, Lu J K, Wei Z, Wang Q, Shen C, Li J, Shen S, Shen J, Yang R, Shi D, Wu H, Wang S, Zhang G 2020 ACS Appl. Mater. Interfaces 12 11945Google Scholar
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[15] Flak J 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications Turin, Italy, Aug. 29−31 2012 p1
[16] Fouda M E, Radwan A G 2014 26th International Conference on Microelectronics (ICM) Doha, Qatar, Dec. 14−17 2014 p172
[17] Pershin Y V, Di Ventra M 2014 Electron. Lett. 50 141Google Scholar
[18] Yi S, ZhenZhen J, XiaoPing W, Yang L 2015 34th Chinese Control Conference (CCC) Hangzhou, China, July 28–30 2015 p3452
[19] Tran S J D, Teuscher C 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Newport, RI, July 25−26 2017 p115
[20] Wang Z, Rao M, Han J W, Zhang J, Lin P, Li Y, Li C, Song W, Asapu S, Midya R, Zhuo Y, Jiang H, Yoon J H, Upadhyay N K, Joshi S, Hu M, Strachan J P, Barnell M, Wu Q, Wu H, Qiu Q, Williams R S, Xia Q, Yang J J 2018 Nat Commun. 9 3208Google Scholar
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