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Metal contamination in process line of superconducting quantum processor chips

XU Xiao ZHANG Haibin SU Feifan YAN Kai RONG Hao DENG Hui YANG Xinying MA Xiaoteng DONG Xue WANG Qiming LIU Jialin LI Manman

Citation:

Metal contamination in process line of superconducting quantum processor chips

XU Xiao, ZHANG Haibin, SU Feifan, YAN Kai, RONG Hao, DENG Hui, YANG Xinying, MA Xiaoteng, DONG Xue, WANG Qiming, LIU Jialin, LI Manman
cstr: 32037.14.aps.75.20251101
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  • The manufacturing process of superconducting quantum processor chips faces special challenges of metal contamination, and their material system and process characteristics are significantly different from those of traditional semiconductor chips. This study focuses on the issue of metal contamination in the fabrication process of quantum chips, systematically analyzing the sources, diffusion mechanisms, and prevention strategies of metal contamination in quantum chips, where the bulk diffusion and surface migration behaviors of superconducting materials (such as Ta, Nb, Al, TiN) on sapphire and silicon substrates are particularly emphasized, aiming to provide theoretical basis and technical references for process optimization and to promote the industrialization process of quantum computing technology.The metal contamination in the fabrication of quantum chips is mainly caused by the metal film materials used in the process, the external environment, or the unintended metal impurity atoms introduced in the manufacturing process. Among them, some quantum chip components directly use superconducting metal materials. Unlike semiconductor chips, they cannot achieve front and back stage isolation, resulting in the continuous presence of metal surface migration channels, and the exposed metal structures on the chip surface. Metal contamination often leads to two basic failure problems: short circuits and leakage currents. These problems mainly result from the bulk diffusion of metal impurities in the dielectric layer and the migration behavior on the sample surface. The diffusion and migration rates of metals are affected by temperature, interface reactions, defects, and grain boundaries. The results show that the sapphire substrate, due to its dense lattice structure, exhibits excellent anti-diffusion performance, reducing the risk of contamination and providing a stable interface environment for superconducting quantum chips. For silicon substrates, special attention must be paid to the contamination risks from high-mobility metals such as Au, In, and Sn. Experimental verification shows that Ti/Au under bump metallization structures on silicon substrates are prone to Au penetration diffusion, and increasing Ti thickness does not significantly improve the blocking effect. The low-temperature process (< 250 ℃) and ultra-low-temperature operating environment (mK level) of quantum chips effectively suppress metal diffusion, but the exposed metal surfaces and material diversity still pose unique challenges.The study recommends establishing a dedicated metal contamination prevention system for quantum chips and proposes future research directions, including the evaluations of novel materials, surface state regulation, and long-term reliability studies. This work provides important theoretical support and technical guidance for optimizing the process and enhancing the performance of superconducting quantum chips.
      Corresponding author: ZHANG Haibin, hbzh@ustc.edu.cn ; SU Feifan, sufeifan@ustc.edu.cn
    • Funds: Project supported by the Natural Science Foundation of Shandong Province, China (Grant No. ZR2022LLZ008), the Jinan Science & Technology Bureau, and the Jinan Innovation Zone, China.
    [1]

    Acharya R, Abanin D A, Aghababaie-Beni L, Aleiner I, Andersen T I, Ansmann M, Arute F, Arya K, Asfaw A, Astrakhantsev N, et al. 2025 Nature 638 920Google Scholar

    [2]

    Gao D X, Fan D J, Zha C, Bei J H, Cai G Q, Cai J B, Cao S R, Chen F S, Chen J, Chen K, et al. 2025 Phys. Rev. Lett. 134 090601Google Scholar

    [3]

    Van Damme J, Massar S, Acharya R, Ivanov T, Perez Lozano D, Canvel Y, Demarets M, Vangoidsenhoven D, Hermans Y, Lai J G, Vadiraj A M, Mongillo M, Wan D, De Boeck J, Potočnik A, De Greve K 2024 Nature 634 74Google Scholar

    [4]

    Dieter K S 2005 Semiconductor Material and Device Characterization (Hoboken: Wiley IEEE Press) p127

    [5]

    Weber E R 1983 Appl. Phys. A 30 1Google Scholar

    [6]

    夸克M, 瑟达 J 著 (韩郑生 译) 2015 半导体制造技术(北京: 电子工业出版社)

    Quirk M, Serda J (translated by Han Z S) 2015 Semiconductor Manufacturing Technology (Beijing: Publishing House of Electronics Industry

    [7]

    Xiao H 2012 Introduction to Semiconductor Manufacturing Technology (Bellingham: SPIE Press

    [8]

    Mehrer H 2007 Diffusion in Solids: Fundamentals, Methods, Materials, Diffusion-Controlled Processes (Heidelberg: Springer Verlag

    [9]

    Seshan K 2012 Handbook of Thin Film Deposition: Techniques, Processes, and Technologies (Amsterdam: Elsevier

    [10]

    Gas P, d'Heurle F M 1993 Appl. Surf. Sci. 73 153Google Scholar

    [11]

    Nicolet M A 1978 Thin Solid Films 52 415Google Scholar

    [12]

    Gösele U, Frank W, Seeger A 1980 Appl. Phys. 23 361Google Scholar

    [13]

    Nakashima K, Iwami M, Hiraki A 1975 Thin Solid Films 25 423Google Scholar

    [14]

    Murarka S P 2005 Diffusion Processes in Advanced Technological Materials (Amsterdam: Elsevier) pp239–281

    [15]

    Saiz E, Cannon R M, Tomsia A P 1999 Acta Mater. 47 4209Google Scholar

    [16]

    Matthews T S, Sawyer C, Ogletree D F, Liliental-Weber Z, Chrzan D C, Wu J 2012 Phys. Rev. Lett. 108 096102Google Scholar

    [17]

    Prabriputaloong K, Piggott M R 1973 J. Am. Ceram. Soc. 56 177Google Scholar

    [18]

    Seebauer E G, Allen C E 1995 Prog. Surf. Sci. 49 265Google Scholar

    [19]

    Kirby K W 2008 M. S. Thesis (State College: The Pennsylvania State University

    [20]

    Wu N J, Yasunaga H, Natori A 1992 Appl. Surf. Sci. 260 75Google Scholar

    [21]

    李智瑞 2012 硕士学位论文 (北京: 北京化工大学)

    Li Z R 2012 M. S. Thesis (Beijing: Beijing University of Chemical Technology

    [22]

    陆裕东, 何小琦, 恩云飞, 王歆, 庄志强 2010 59 3438Google Scholar

    Lu Y D, He X Q, En Y F, Wang X, Zhuang Z Q 2010 Acta Phys. Sin. 59 3438Google Scholar

  • 图 1  半导体芯片TaN/TiN等金属扩散阻挡层和硅化物NiSi接触层示意图[7]

    Figure 1.  Schematic diagram of TaN/TiN diffusion barrier layers and NiSi contact layer in semiconductor chips[7].

    图 2  用于量子芯片的CPW传输线及其地线互连的铝质跨接桥结构

    Figure 2.  Aluminum crossover bridge structure for CPW transmission line and ground interconnects in quantum chips.

    图 3  梳状电极UBM结构的线间电阻测试示意图

    Figure 3.  Schematic of interline resistance test structure for comb-shaped UBM electrodes.

    图 4  高温处理(245 ℃/5 min)前后UBM线间电阻变化对比

    Figure 4.  Comparison of UBM interline resistance before and after thermal treatment (245 ℃/5 min).

    表 1  半导体芯片与超导量子芯片的工艺比较

    Table 1.  Comparison of process characteristics between conventional semiconductor chips and superconducting quantum chips.

    半导体芯片 超导量子芯片
    器件 CMOS场效应晶体管等 约瑟夫森结的Transmon结构等
    材料 衬底 Si, InP, SiC等 蓝宝石、高阻Si等
    前道工艺 半导体掺杂等 超导金属、少量介质材料等
    工艺 离子注入、热工艺等 有机清洗工艺、剥离工艺等
    环境 温度 –40—150 ℃ 毫开尔文(mK)级低温
    湿度 常规环境30%—70% RH或更宽泛 真空环境
    电磁 常规环境 (除空间应用等特殊场景外) 电磁屏蔽
    DownLoad: CSV

    表 2  体扩散与表面扩散的特性对比[18]

    Table 2.  Comparison of physical characteristics between metal bulk diffusion and surface migration[18].

    特性体扩散表面扩散
    激活能较高(1—5 eV)较低(0.1—2.0 eV)
    温度依赖性较敏感更敏感(指数关系)
    主导机制空位、间隙跳跃、交换
    典型速率较慢更快(Ds≫Dbulk)
    DownLoad: CSV
    Baidu
  • [1]

    Acharya R, Abanin D A, Aghababaie-Beni L, Aleiner I, Andersen T I, Ansmann M, Arute F, Arya K, Asfaw A, Astrakhantsev N, et al. 2025 Nature 638 920Google Scholar

    [2]

    Gao D X, Fan D J, Zha C, Bei J H, Cai G Q, Cai J B, Cao S R, Chen F S, Chen J, Chen K, et al. 2025 Phys. Rev. Lett. 134 090601Google Scholar

    [3]

    Van Damme J, Massar S, Acharya R, Ivanov T, Perez Lozano D, Canvel Y, Demarets M, Vangoidsenhoven D, Hermans Y, Lai J G, Vadiraj A M, Mongillo M, Wan D, De Boeck J, Potočnik A, De Greve K 2024 Nature 634 74Google Scholar

    [4]

    Dieter K S 2005 Semiconductor Material and Device Characterization (Hoboken: Wiley IEEE Press) p127

    [5]

    Weber E R 1983 Appl. Phys. A 30 1Google Scholar

    [6]

    夸克M, 瑟达 J 著 (韩郑生 译) 2015 半导体制造技术(北京: 电子工业出版社)

    Quirk M, Serda J (translated by Han Z S) 2015 Semiconductor Manufacturing Technology (Beijing: Publishing House of Electronics Industry

    [7]

    Xiao H 2012 Introduction to Semiconductor Manufacturing Technology (Bellingham: SPIE Press

    [8]

    Mehrer H 2007 Diffusion in Solids: Fundamentals, Methods, Materials, Diffusion-Controlled Processes (Heidelberg: Springer Verlag

    [9]

    Seshan K 2012 Handbook of Thin Film Deposition: Techniques, Processes, and Technologies (Amsterdam: Elsevier

    [10]

    Gas P, d'Heurle F M 1993 Appl. Surf. Sci. 73 153Google Scholar

    [11]

    Nicolet M A 1978 Thin Solid Films 52 415Google Scholar

    [12]

    Gösele U, Frank W, Seeger A 1980 Appl. Phys. 23 361Google Scholar

    [13]

    Nakashima K, Iwami M, Hiraki A 1975 Thin Solid Films 25 423Google Scholar

    [14]

    Murarka S P 2005 Diffusion Processes in Advanced Technological Materials (Amsterdam: Elsevier) pp239–281

    [15]

    Saiz E, Cannon R M, Tomsia A P 1999 Acta Mater. 47 4209Google Scholar

    [16]

    Matthews T S, Sawyer C, Ogletree D F, Liliental-Weber Z, Chrzan D C, Wu J 2012 Phys. Rev. Lett. 108 096102Google Scholar

    [17]

    Prabriputaloong K, Piggott M R 1973 J. Am. Ceram. Soc. 56 177Google Scholar

    [18]

    Seebauer E G, Allen C E 1995 Prog. Surf. Sci. 49 265Google Scholar

    [19]

    Kirby K W 2008 M. S. Thesis (State College: The Pennsylvania State University

    [20]

    Wu N J, Yasunaga H, Natori A 1992 Appl. Surf. Sci. 260 75Google Scholar

    [21]

    李智瑞 2012 硕士学位论文 (北京: 北京化工大学)

    Li Z R 2012 M. S. Thesis (Beijing: Beijing University of Chemical Technology

    [22]

    陆裕东, 何小琦, 恩云飞, 王歆, 庄志强 2010 59 3438Google Scholar

    Lu Y D, He X Q, En Y F, Wang X, Zhuang Z Q 2010 Acta Phys. Sin. 59 3438Google Scholar

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Publishing process
  • Received Date:  15 August 2025
  • Accepted Date:  17 September 2025
  • Available Online:  13 December 2025
  • Published Online:  05 January 2026
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