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The non-ideal characteristics such as dielectric loss and skin effect of coaxial cables etc can cause attenuation of the high-frequency component of the signals, making it difficult for the receiver to interpret the signal, thereby greatly reducing the data rate. Pulse width modulation (PWM) pre-emphasis technique, which has been very good to use in the binary signal, utilizes time-domain information processing to increase the data rate. We introduce the new adaptive PWM pre-emphasis method to further eliminate the data-dependent jitter, which can dynamically compensate for the transmission loss of multiple-valued data with strong or weak pre-emphasis. The results of eye diagrams show that this method can improve the quality of signal transmission.
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Keywords:
- pulse-width modulation /
- multiple-valued data /
- data transmission /
- pre-emphasis
[1] Kudoh Y, Fukaishi M, Mizuno M 2003 IEEE J. Solid-State Circuits 38 741
[2] Gai W, Hidaka Y, Koyana Gi Y, Jiang J H, Osone H, Horie T 2004 Symposium on VLSI Circuits, Digest of Technical Papers, June 17-19, 2004 p138
[3] Xu H H, Huang Q Z, Li Y T 2010 Chin.. Phys. B 19 084210
[4] Li Y, Cheng H R, Li W, Yu S H, Yang Z 2012 Acta Phys. Sin. 61 194205 in Chinese 2012 61 194205 (in Chinese) [李源, 成浩然, 李蔚, 余少华 杨铸 2012 61 194205]
[5] Schrader J, Klumperink E, Visschers J, Nauta B 2005 Symposium on VLSI Circuits June 16-18, 2005 p388
[6] Yuminaka Y, Takahashi Y 2008 Multiple Valued Logic Dallas, May 22-24, 2008 p20
[7] Yuminaka Y, Takahashi Y, Henmi K 2009 39th International Symposium on Multiple-Valued Logic Naha, Okinawa, May 21-23, 2009 p250
[8] Yang F X, Zhang D M, Deng Z W 2008 Acta Phys. Sin. 57 3845 (in Chinese) [杨凤霞, 张端明, 邓宗伟 2008 57 3845]
[9] Yuminaka, Yamamura 2007 Mutiple-Valued Logic IEEE Oslo, May 13-16, 2007 p26
[10] Horace Cheng, Anthony Chan Carusone Member 2008 Custom Integrated Circuits Conference San Jose CA September 21-24, 2008 p635
[11] Jan-Rutger (J. H. R.) Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta 2006 Custom Integrated Circuits Conference San Jose CA p591
[12] Yuminaka, Takahashi 2008 Multiple Valued Logic p20
[13] Yuminaka, Henmi 2010 Communications and Information Technologies Tokyo, October 26-29, 2010 p1103
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[1] Kudoh Y, Fukaishi M, Mizuno M 2003 IEEE J. Solid-State Circuits 38 741
[2] Gai W, Hidaka Y, Koyana Gi Y, Jiang J H, Osone H, Horie T 2004 Symposium on VLSI Circuits, Digest of Technical Papers, June 17-19, 2004 p138
[3] Xu H H, Huang Q Z, Li Y T 2010 Chin.. Phys. B 19 084210
[4] Li Y, Cheng H R, Li W, Yu S H, Yang Z 2012 Acta Phys. Sin. 61 194205 in Chinese 2012 61 194205 (in Chinese) [李源, 成浩然, 李蔚, 余少华 杨铸 2012 61 194205]
[5] Schrader J, Klumperink E, Visschers J, Nauta B 2005 Symposium on VLSI Circuits June 16-18, 2005 p388
[6] Yuminaka Y, Takahashi Y 2008 Multiple Valued Logic Dallas, May 22-24, 2008 p20
[7] Yuminaka Y, Takahashi Y, Henmi K 2009 39th International Symposium on Multiple-Valued Logic Naha, Okinawa, May 21-23, 2009 p250
[8] Yang F X, Zhang D M, Deng Z W 2008 Acta Phys. Sin. 57 3845 (in Chinese) [杨凤霞, 张端明, 邓宗伟 2008 57 3845]
[9] Yuminaka, Yamamura 2007 Mutiple-Valued Logic IEEE Oslo, May 13-16, 2007 p26
[10] Horace Cheng, Anthony Chan Carusone Member 2008 Custom Integrated Circuits Conference San Jose CA September 21-24, 2008 p635
[11] Jan-Rutger (J. H. R.) Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta 2006 Custom Integrated Circuits Conference San Jose CA p591
[12] Yuminaka, Takahashi 2008 Multiple Valued Logic p20
[13] Yuminaka, Henmi 2010 Communications and Information Technologies Tokyo, October 26-29, 2010 p1103
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