Based on the influence of the nonuniform temperature distribution and the inductance effect of the wires on the interconnect delay time, a zero-clock-skew construction method of RLC interconnect clock tree is presented in this paper. The proposed analytical model has closed form expression and takes temperature distribution, inductance effect and unsymmetrical interconnect structure into consideration. Adopting parameters of 65 nm process technology, the proposed model is compared with the other available similar models. Results show that the new model is more accurate with maximum 1% error.